ath9k: AR9380 PAPRD changes to improve tx performance

chromeos/compat-wireless/drivers/net/wireless/ath/ath9k/hw.h

 /*
  * Copyright (c) 2008-2010 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
  * copyright notice and this permission notice appear in all copies.
  *
  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@@ skipping 817 matching lines @@
         struct ar9003_txs *ts_ring;
         void *ts_start;
         u32 ts_paddr_start;
         u32 ts_paddr_end;
         u16 ts_tail;
         u8 ts_size;
 
         u32 bb_watchdog_last_status;
         u32 bb_watchdog_timeout_ms; /* in ms, 0 to disable */
 
+        unsigned int paprd_target_power;
+        unsigned int paprd_training_power;
+        unsigned int paprd_ratemask;
+        unsigned int paprd_ratemask_ht40;
+        bool paprd_table_write_done;
         u32 paprd_gain_table_entries[PAPRD_GAIN_TABLE_ENTRIES];
         u8 paprd_gain_table_index[PAPRD_GAIN_TABLE_ENTRIES];
         /*
          * Store the permanent value of Reg 0x4004in WARegVal
          * so we dont have to R/M/W. We should not be reading
          * this register when in sleep states.
          */
         u32 WARegVal;
 
         /* Enterprise mode cap */
@@ skipping 19 matching lines @@
 {
         return &ah->ops;
 }
 
 static inline int sign_extend(int val, const int nbits)
 {
         int order = BIT(nbits-1);
         return (val ^ order) - order;
 }
 
+static inline u8 get_streams(int mask)
+{
+        return !!(mask & BIT(0)) + !!(mask & BIT(1)) + !!(mask & BIT(2));
+}
+
 /* Initialization, Detach, Reset */
 const char *ath9k_hw_probe(u16 vendorid, u16 devid);
 void ath9k_hw_deinit(struct ath_hw *ah);
 int ath9k_hw_init(struct ath_hw *ah);
 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
                    struct ath9k_hw_cal_data *caldata, bool bChannelChange);
 int ath9k_hw_fill_cap_info(struct ath_hw *ah);
 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan);
 
 /* Key Cache Management */
@@ skipping 121 matching lines @@
 #define ATH_PCIE_CAP_LINK_CTRL  0x70
 #define ATH_PCIE_CAP_LINK_L0S   1
 #define ATH_PCIE_CAP_LINK_L1    2
 
 #define ATH9K_CLOCK_RATE_CCK            22
 #define ATH9K_CLOCK_RATE_5GHZ_OFDM      40
 #define ATH9K_CLOCK_RATE_2GHZ_OFDM      44
 #define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM 44
 
 #endif