chromeos/compat-wireless/drivers/net/wireless/ath/ath9k/ar9003_phy.h - Issue 5990016: ath9k: AR9380 PAPRD changes to improve tx performance

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Side by Side Diff: chromeos/compat-wireless/drivers/net/wireless/ath/ath9k/ar9003_phy.h

Issue 5990016: ath9k: AR9380 PAPRD changes to improve tx performance (Closed) Base URL: ssh://git@gitrw.chromium.org:9222/kernel.git@master

Patch Set: Created 9 years, 11 months ago

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1 /*	1 /*

2 * Copyright (c) 2002-2010 Atheros Communications, Inc.	2 * Copyright (c) 2002-2010 Atheros Communications, Inc.

3 *	3 *

4 * Permission to use, copy, modify, and/or distribute this software for any	4 * Permission to use, copy, modify, and/or distribute this software for any

5 * purpose with or without fee is hereby granted, provided that the above	5 * purpose with or without fee is hereby granted, provided that the above

6 * copyright notice and this permission notice appear in all copies.	6 * copyright notice and this permission notice appear in all copies.

7 *	7 *

8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES	8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES

9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF	9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF

10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR	10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR

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1033 #define AR_PHY_PA_GAIN123_B0 (AR_CHAN_BASE + 0xf8)	1033 #define AR_PHY_PA_GAIN123_B0 (AR_CHAN_BASE + 0xf8)

1034 #define AR_PHY_PA_GAIN123_B1 (AR_CHAN1_BASE + 0xf8)	1034 #define AR_PHY_PA_GAIN123_B1 (AR_CHAN1_BASE + 0xf8)

1035 #define AR_PHY_PA_GAIN123_B2 (AR_CHAN2_BASE + 0xf8)	1035 #define AR_PHY_PA_GAIN123_B2 (AR_CHAN2_BASE + 0xf8)

1036 #define AR_PHY_PA_GAIN123_PA_GAIN1 0x3FF	1036 #define AR_PHY_PA_GAIN123_PA_GAIN1 0x3FF

1037 #define AR_PHY_PA_GAIN123_PA_GAIN1_S 0	1037 #define AR_PHY_PA_GAIN123_PA_GAIN1_S 0

1038	1038

1039 #define AR_PHY_POWERTX_RATE5 (AR_SM_BASE + 0x1d0)	1039 #define AR_PHY_POWERTX_RATE5 (AR_SM_BASE + 0x1d0)

1040 #define AR_PHY_POWERTX_RATE5_POWERTXHT20_0 0x3F	1040 #define AR_PHY_POWERTX_RATE5_POWERTXHT20_0 0x3F

1041 #define AR_PHY_POWERTX_RATE5_POWERTXHT20_0_S 0	1041 #define AR_PHY_POWERTX_RATE5_POWERTXHT20_0_S 0

1042	1042

	1043 #define AR_PHY_POWERTX_RATE6 (AR_SM_BASE + 0x1d4)

	1044 #define AR_PHY_POWERTX_RATE6_POWERTXHT20_5 0x3F00

	1045 #define AR_PHY_POWERTX_RATE6_POWERTXHT20_5_S 8

	1046

	1047 #define AR_PHY_POWERTX_RATE8 (AR_SM_BASE + 0x1dc)

	1048 #define AR_PHY_POWERTX_RATE8_POWERTXHT40_5 0x3F00

	1049 #define AR_PHY_POWERTX_RATE8_POWERTXHT40_5_S 8

	1050

1043 void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx);	1051 void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx);

1044	1052

1045 #endif /* AR9003_PHY_H */	1053 #endif /* AR9003_PHY_H */

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