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1 /* | 1 /* |
2 * Copyright (c) 2010 Atheros Communications Inc. | 2 * Copyright (c) 2010 Atheros Communications Inc. |
3 * | 3 * |
4 * Permission to use, copy, modify, and/or distribute this software for any | 4 * Permission to use, copy, modify, and/or distribute this software for any |
5 * purpose with or without fee is hereby granted, provided that the above | 5 * purpose with or without fee is hereby granted, provided that the above |
6 * copyright notice and this permission notice appear in all copies. | 6 * copyright notice and this permission notice appear in all copies. |
7 * | 7 * |
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
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627 const u32 txiqcal_status[AR9300_MAX_CHAINS] = { | 627 const u32 txiqcal_status[AR9300_MAX_CHAINS] = { |
628 AR_PHY_TX_IQCAL_STATUS_B0, | 628 AR_PHY_TX_IQCAL_STATUS_B0, |
629 AR_PHY_TX_IQCAL_STATUS_B1, | 629 AR_PHY_TX_IQCAL_STATUS_B1, |
630 AR_PHY_TX_IQCAL_STATUS_B2, | 630 AR_PHY_TX_IQCAL_STATUS_B2, |
631 }; | 631 }; |
632 const u32 tx_corr_coeff[AR9300_MAX_CHAINS] = { | 632 const u32 tx_corr_coeff[AR9300_MAX_CHAINS] = { |
633 AR_PHY_TX_IQCAL_CORR_COEFF_01_B0, | 633 AR_PHY_TX_IQCAL_CORR_COEFF_01_B0, |
634 AR_PHY_TX_IQCAL_CORR_COEFF_01_B1, | 634 AR_PHY_TX_IQCAL_CORR_COEFF_01_B1, |
635 AR_PHY_TX_IQCAL_CORR_COEFF_01_B2, | 635 AR_PHY_TX_IQCAL_CORR_COEFF_01_B2, |
636 }; | 636 }; |
637 const u32 rx_corr[AR9300_MAX_CHAINS] = { | |
638 AR_PHY_RX_IQCAL_CORR_B0, | |
639 AR_PHY_RX_IQCAL_CORR_B1, | |
640 AR_PHY_RX_IQCAL_CORR_B2, | |
641 }; | |
642 const u_int32_t chan_info_tab[] = { | 637 const u_int32_t chan_info_tab[] = { |
643 AR_PHY_CHAN_INFO_TAB_0, | 638 AR_PHY_CHAN_INFO_TAB_0, |
644 AR_PHY_CHAN_INFO_TAB_1, | 639 AR_PHY_CHAN_INFO_TAB_1, |
645 AR_PHY_CHAN_INFO_TAB_2, | 640 AR_PHY_CHAN_INFO_TAB_2, |
646 }; | 641 }; |
647 s32 iq_res[6]; | 642 s32 iq_res[6]; |
648 s32 iqc_coeff[2]; | 643 s32 iqc_coeff[2]; |
649 s32 i, j; | 644 s32 i, j; |
650 u32 num_chains = 0; | 645 u32 num_chains = 0; |
651 | 646 |
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709 goto TX_IQ_CAL_FAILED; | 704 goto TX_IQ_CAL_FAILED; |
710 } | 705 } |
711 | 706 |
712 ath_print(common, ATH_DBG_CALIBRATE, | 707 ath_print(common, ATH_DBG_CALIBRATE, |
713 "IQ_COEFF[0] = 0x%x IQ_COEFF[1] = 0x%x\n", | 708 "IQ_COEFF[0] = 0x%x IQ_COEFF[1] = 0x%x\n", |
714 iqc_coeff[0], iqc_coeff[1]); | 709 iqc_coeff[0], iqc_coeff[1]); |
715 | 710 |
716 REG_RMW_FIELD(ah, tx_corr_coeff[i], | 711 REG_RMW_FIELD(ah, tx_corr_coeff[i], |
717 AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE, | 712 AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE, |
718 iqc_coeff[0]); | 713 iqc_coeff[0]); |
719 REG_RMW_FIELD(ah, rx_corr[i], | |
720 AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_Q_COFF, | |
721 iqc_coeff[1] >> 7); | |
722 REG_RMW_FIELD(ah, rx_corr[i], | |
723 AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_I_COFF, | |
724 iqc_coeff[1]); | |
725 } | 714 } |
726 | 715 |
727 REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_3, | 716 REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_3, |
728 AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN, 0x1); | 717 AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN, 0x1); |
729 REG_RMW_FIELD(ah, AR_PHY_RX_IQCAL_CORR_B0, | |
730 AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN, 0x1); | |
731 | 718 |
732 return; | 719 return; |
733 | 720 |
734 TX_IQ_CAL_FAILED: | 721 TX_IQ_CAL_FAILED: |
735 ath_print(common, ATH_DBG_CALIBRATE, "Tx IQ Cal failed\n"); | 722 ath_print(common, ATH_DBG_CALIBRATE, "Tx IQ Cal failed\n"); |
736 } | 723 } |
737 | 724 |
738 static bool ar9003_hw_init_cal(struct ath_hw *ah, | 725 static bool ar9003_hw_init_cal(struct ath_hw *ah, |
739 struct ath9k_channel *chan) | 726 struct ath9k_channel *chan) |
740 { | 727 { |
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812 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah); | 799 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah); |
813 struct ath_hw_ops *ops = ath9k_hw_ops(ah); | 800 struct ath_hw_ops *ops = ath9k_hw_ops(ah); |
814 | 801 |
815 priv_ops->init_cal_settings = ar9003_hw_init_cal_settings; | 802 priv_ops->init_cal_settings = ar9003_hw_init_cal_settings; |
816 priv_ops->init_cal = ar9003_hw_init_cal; | 803 priv_ops->init_cal = ar9003_hw_init_cal; |
817 priv_ops->setup_calibration = ar9003_hw_setup_calibration; | 804 priv_ops->setup_calibration = ar9003_hw_setup_calibration; |
818 priv_ops->iscal_supported = ar9003_hw_iscal_supported; | 805 priv_ops->iscal_supported = ar9003_hw_iscal_supported; |
819 | 806 |
820 ops->calibrate = ar9003_hw_calibrate; | 807 ops->calibrate = ar9003_hw_calibrate; |
821 } | 808 } |
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