Subzero: Automatically infer regalloc preferences and overlap.

src/llvm2ice.cpp

 //===- subzero/src/llvm2ice.cpp - Driver for testing ----------------------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file defines a driver that uses LLVM capabilities to parse a
@@ skipping 29 matching lines @@
         clEnumValN(Ice::IceV_Preds, "pred", "Show predecessors"),
         clEnumValN(Ice::IceV_Succs, "succ", "Show successors"),
         clEnumValN(Ice::IceV_Liveness, "live", "Liveness information"),
         clEnumValN(Ice::IceV_RegManager, "rmgr", "Register manager status"),
         clEnumValN(Ice::IceV_RegOrigins, "orig", "Physical register origins"),
         clEnumValN(Ice::IceV_LinearScan, "regalloc", "Linear scan details"),
         clEnumValN(Ice::IceV_Frame, "frame", "Stack frame layout details"),
         clEnumValN(Ice::IceV_Timing, "time", "Pass timing details"),
         clEnumValN(Ice::IceV_AddrOpt, "addropt", "Address mode optimization"),
         clEnumValN(Ice::IceV_All, "all", "Use all verbose options"),
+        clEnumValN(Ice::IceV_Most, "most",
+                   "Use all verbose options except 'regalloc' and 'time'"),
         clEnumValN(Ice::IceV_None, "none", "No verbosity"), clEnumValEnd));
 static cl::opt<Ice::TargetArch> TargetArch(
     "target", cl::desc("Target architecture:"), cl::init(Ice::Target_X8632),
     cl::values(
         clEnumValN(Ice::Target_X8632, "x8632", "x86-32"),
         clEnumValN(Ice::Target_X8632, "x86-32", "x86-32 (same as x8632)"),
         clEnumValN(Ice::Target_X8632, "x86_32", "x86-32 (same as x8632)"),
         clEnumValN(Ice::Target_X8664, "x8664", "x86-64"),
         clEnumValN(Ice::Target_X8664, "x86-64", "x86-64 (same as x8664)"),
         clEnumValN(Ice::Target_X8664, "x86_64", "x86-64 (same as x8664)"),
@@ skipping 67 matching lines @@
 
 static cl::opt<bool>
 BuildOnRead("build-on-read",
             cl::desc("Build ICE instructions when reading bitcode"),
             cl::init(false));
 
 static cl::opt<bool>
     UseIntegratedAssembler("integrated-as",
                            cl::desc("Use integrated assembler (default yes)"),
                            cl::init(true));
+static cl::alias UseIas("ias", cl::desc("Alias for -integrated-as"),
+                        cl::NotHidden, cl::aliasopt(UseIntegratedAssembler));
 
 int main(int argc, char **argv) {
 
   cl::ParseCommandLineOptions(argc, argv);
 
   Ice::VerboseMask VMask = Ice::IceV_None;
   for (unsigned i = 0; i != VerboseList.size(); ++i)
     VMask |= VerboseList[i];
 
   std::ofstream Ofs;
@@ skipping 48 matching lines @@
     }
 
     Ice::Converter Converter(Mod, &Ctx, Flags);
     Converter.convertToIce();
     ErrorStatus = Converter.getErrorStatus();
   }
   const bool FinalStats = true;
   Ctx.dumpStats("_FINAL_", FinalStats);
   return ErrorStatus;
 }