Subzero: Automatically infer regalloc preferences and overlap.

src/IceInstX8632.def

 //===- subzero/src/IceInstX8632.def - X-macros for x86-32 insts -*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file defines properties of lowered x86-32 instructions in the
@@ skipping 26 matching lines @@
   X(Reg_xmm5, = Reg_xmm0 + 5, "xmm5", ""  , ""  , 1, 0, 0, 0, 0, 0, 1)  \
   X(Reg_xmm6, = Reg_xmm0 + 6, "xmm6", ""  , ""  , 1, 0, 0, 0, 0, 0, 1)  \
   X(Reg_xmm7, = Reg_xmm0 + 7, "xmm7", ""  , ""  , 1, 0, 0, 0, 0, 0, 1)  \
 //#define X(val, encode, name, name16, name8, scratch, preserved, stackptr,
 //          frameptr, isI8, isInt, isFP)
 
 // We also provide a combined table, so that there is a namespace where
 // all of the registers are considered and have distinct numberings.
 // This is in contrast to the above, where the "encode" is based on how
 // the register numbers will be encoded in binaries and values can overlap.
+// Note that the isI8 attributed of Reg_ah is not set.  In general we
+// don't want the register allocator choosing Reg_ah, in particular
+// for lowering insertelement to pinsrb where internally we use an
+// 8-bit operand but externally pinsrb uses a 32-bit register, in
+// which Reg_ah doesn't map to eax.
 #define REGX8632_TABLE                                                  \
   /* val, encode, name, name16, name8, scratch, preserved, stackptr,    \
      frameptr, isI8, isInt, isFP */                                     \
   REGX8632_GPR_TABLE                                                    \
-  X(Reg_ah,  = Reg_eax + 4,   "???",  ""  , "ah", 0, 0, 0, 0, 1, 0, 0)  \
+  X(Reg_ah,  = Reg_eax + 4,   "???",  ""  , "ah", 0, 0, 0, 0, 0, 0, 0)  \
   REGX8632_XMM_TABLE
 //#define X(val, encode, name, name16, name8, scratch, preserved, stackptr,
 //          frameptr, isI8, isInt, isFP)
 
 #define REGX8632_TABLE_BOUNDS                                           \
   /* val, init */                                                       \
   X(Reg_GPR_First, = Reg_eax)                                           \
   X(Reg_GPR_Last,  = Reg_edi)                                           \
   X(Reg_XMM_First, = Reg_xmm0)                                          \
   X(Reg_XMM_Last,  = Reg_xmm7)                                          \
@@ skipping 66 matching lines @@
   X(IceType_v4i1,  IceType_i32 , "?" , ""  , "d",  "xmmword ptr") \
   X(IceType_v8i1,  IceType_i16 , "?" , ""  , "w",  "xmmword ptr") \
   X(IceType_v16i1, IceType_i8  , "?" , ""  , "b",  "xmmword ptr") \
   X(IceType_v16i8, IceType_i8  , "?" , ""  , "b",  "xmmword ptr") \
   X(IceType_v8i16, IceType_i16 , "?" , ""  , "w",  "xmmword ptr") \
   X(IceType_v4i32, IceType_i32 , "dq", ""  , "d",  "xmmword ptr") \
   X(IceType_v4f32, IceType_f32 , "ps", ""  , "" ,  "xmmword ptr") \
 //#define X(tag, elementty, cvt, sdss, width)
 
 #endif // SUBZERO_SRC_ICEINSTX8632_DEF