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Side by Side Diff: src/compiler/ia32/instruction-codes-ia32.h

Issue 596703004: [turbofan] Add backend support for float32. (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: REBASE Created 6 years, 3 months ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #ifndef V8_COMPILER_IA32_INSTRUCTION_CODES_IA32_H_ 5 #ifndef V8_COMPILER_IA32_INSTRUCTION_CODES_IA32_H_
6 #define V8_COMPILER_IA32_INSTRUCTION_CODES_IA32_H_ 6 #define V8_COMPILER_IA32_INSTRUCTION_CODES_IA32_H_
7 7
8 namespace v8 { 8 namespace v8 {
9 namespace internal { 9 namespace internal {
10 namespace compiler { 10 namespace compiler {
(...skipping 17 matching lines...) Expand all
28 V(IA32Shr) \ 28 V(IA32Shr) \
29 V(IA32Sar) \ 29 V(IA32Sar) \
30 V(IA32Ror) \ 30 V(IA32Ror) \
31 V(SSEFloat64Cmp) \ 31 V(SSEFloat64Cmp) \
32 V(SSEFloat64Add) \ 32 V(SSEFloat64Add) \
33 V(SSEFloat64Sub) \ 33 V(SSEFloat64Sub) \
34 V(SSEFloat64Mul) \ 34 V(SSEFloat64Mul) \
35 V(SSEFloat64Div) \ 35 V(SSEFloat64Div) \
36 V(SSEFloat64Mod) \ 36 V(SSEFloat64Mod) \
37 V(SSEFloat64Sqrt) \ 37 V(SSEFloat64Sqrt) \
38 V(SSECvtss2sd) \
39 V(SSECvtsd2ss) \
38 V(SSEFloat64ToInt32) \ 40 V(SSEFloat64ToInt32) \
39 V(SSEFloat64ToUint32) \ 41 V(SSEFloat64ToUint32) \
40 V(SSEInt32ToFloat64) \ 42 V(SSEInt32ToFloat64) \
41 V(SSEUint32ToFloat64) \ 43 V(SSEUint32ToFloat64) \
42 V(IA32Movsxbl) \ 44 V(IA32Movsxbl) \
43 V(IA32Movzxbl) \ 45 V(IA32Movzxbl) \
44 V(IA32Movb) \ 46 V(IA32Movb) \
45 V(IA32Movsxwl) \ 47 V(IA32Movsxwl) \
46 V(IA32Movzxwl) \ 48 V(IA32Movzxwl) \
47 V(IA32Movw) \ 49 V(IA32Movw) \
(...skipping 27 matching lines...) Expand all
75 V(MR1I) /* [%r0 + %r1 * 1 + K] */ \ 77 V(MR1I) /* [%r0 + %r1 * 1 + K] */ \
76 V(MR2I) /* [%r0 + %r1 * 2 + K] */ \ 78 V(MR2I) /* [%r0 + %r1 * 2 + K] */ \
77 V(MR4I) /* [%r0 + %r1 * 4 + K] */ \ 79 V(MR4I) /* [%r0 + %r1 * 4 + K] */ \
78 V(MR8I) /* [%r0 + %r1 * 8 + K] */ 80 V(MR8I) /* [%r0 + %r1 * 8 + K] */
79 81
80 } // namespace compiler 82 } // namespace compiler
81 } // namespace internal 83 } // namespace internal
82 } // namespace v8 84 } // namespace v8
83 85
84 #endif // V8_COMPILER_IA32_INSTRUCTION_CODES_IA32_H_ 86 #endif // V8_COMPILER_IA32_INSTRUCTION_CODES_IA32_H_
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