src/compiler/arm/instruction-codes-arm.h - Issue 596703004: [turbofan] Add backend support for float32.

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Side by Side Diff: src/compiler/arm/instruction-codes-arm.h

Issue 596703004: [turbofan] Add backend support for float32. (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge

Patch Set: REBASE Created 6 years, 2 months ago

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1 // Copyright 2014 the V8 project authors. All rights reserved.	1 // Copyright 2014 the V8 project authors. All rights reserved.

2 // Use of this source code is governed by a BSD-style license that can be	2 // Use of this source code is governed by a BSD-style license that can be

3 // found in the LICENSE file.	3 // found in the LICENSE file.

4	4

5 #ifndef V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_	5 #ifndef V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_

6 #define V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_	6 #define V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_

7	7

8 namespace v8 {	8 namespace v8 {

9 namespace internal {	9 namespace internal {

10 namespace compiler {	10 namespace compiler {

(...skipping 24 matching lines...) Expand all Loading...
35 V(ArmVcmpF64) \	35 V(ArmVcmpF64) \

36 V(ArmVaddF64) \	36 V(ArmVaddF64) \

37 V(ArmVsubF64) \	37 V(ArmVsubF64) \

38 V(ArmVmulF64) \	38 V(ArmVmulF64) \

39 V(ArmVmlaF64) \	39 V(ArmVmlaF64) \

40 V(ArmVmlsF64) \	40 V(ArmVmlsF64) \

41 V(ArmVdivF64) \	41 V(ArmVdivF64) \

42 V(ArmVmodF64) \	42 V(ArmVmodF64) \

43 V(ArmVnegF64) \	43 V(ArmVnegF64) \

44 V(ArmVsqrtF64) \	44 V(ArmVsqrtF64) \

	45 V(ArmVcvtF32F64) \

	46 V(ArmVcvtF64F32) \

45 V(ArmVcvtF64S32) \	47 V(ArmVcvtF64S32) \

46 V(ArmVcvtF64U32) \	48 V(ArmVcvtF64U32) \

47 V(ArmVcvtS32F64) \	49 V(ArmVcvtS32F64) \

48 V(ArmVcvtU32F64) \	50 V(ArmVcvtU32F64) \

49 V(ArmVldr32) \	51 V(ArmVldrF32) \

50 V(ArmVstr32) \	52 V(ArmVstrF32) \

51 V(ArmVldr64) \	53 V(ArmVldrF64) \

52 V(ArmVstr64) \	54 V(ArmVstrF64) \

53 V(ArmLdrb) \	55 V(ArmLdrb) \

54 V(ArmLdrsb) \	56 V(ArmLdrsb) \

55 V(ArmStrb) \	57 V(ArmStrb) \

56 V(ArmLdrh) \	58 V(ArmLdrh) \

57 V(ArmLdrsh) \	59 V(ArmLdrsh) \

58 V(ArmStrh) \	60 V(ArmStrh) \

59 V(ArmLdr) \	61 V(ArmLdr) \

60 V(ArmStr) \	62 V(ArmStr) \

61 V(ArmPush) \	63 V(ArmPush) \

62 V(ArmStoreWriteBarrier)	64 V(ArmStoreWriteBarrier)

(...skipping 15 matching lines...) Expand all Loading...
78 V(Operand2_R_ASR_R) /* %r0 ASR %r1 */ \	80 V(Operand2_R_ASR_R) /* %r0 ASR %r1 */ \

79 V(Operand2_R_LSL_R) /* %r0 LSL %r1 */ \	81 V(Operand2_R_LSL_R) /* %r0 LSL %r1 */ \

80 V(Operand2_R_LSR_R) /* %r0 LSR %r1 */ \	82 V(Operand2_R_LSR_R) /* %r0 LSR %r1 */ \

81 V(Operand2_R_ROR_R) /* %r0 ROR %r1 */	83 V(Operand2_R_ROR_R) /* %r0 ROR %r1 */

82	84

83 } // namespace compiler	85 } // namespace compiler

84 } // namespace internal	86 } // namespace internal

85 } // namespace v8	87 } // namespace v8

86	88

87 #endif // V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_	89 #endif // V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_

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