Merge (x & y) == 0 pattern to emit a single test instruction.

runtime/vm/assembler_mips.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/globals.h"
 #if defined(TARGET_ARCH_MIPS)
 
 #include "vm/assembler.h"
 #include "vm/longjump.h"
 #include "vm/runtime_entry.h"
@@ skipping 349 matching lines @@
     } else {
       lw(rd, Address(PP, offset_low));
     }
   }
 }
 
 
 void Assembler::AdduDetectOverflow(Register rd, Register rs, Register rt,
                                    Register ro, Register scratch) {
   ASSERT(rd != ro);
-  ASSERT(rd != TMP1);
-  ASSERT(ro != TMP1);
+  ASSERT(rd != TMP);
+  ASSERT(ro != TMP);
   ASSERT(ro != rs);
   ASSERT(ro != rt);
 
   if ((rs == rt) && (rd == rs)) {
     ASSERT(scratch != kNoRegister);
-    ASSERT(scratch != TMP1);
+    ASSERT(scratch != TMP);
     ASSERT(rd != scratch);
     ASSERT(ro != scratch);
     ASSERT(rs != scratch);
     ASSERT(rt != scratch);
     mov(scratch, rt);
     rt = scratch;
   }
 
   if (rd == rs) {
-    mov(TMP1, rs);  // Preserve rs.
+    mov(TMP, rs);  // Preserve rs.
     addu(rd, rs, rt);  // rs is overwritten.
-    xor_(TMP1, rd, TMP1);  // Original rs.
+    xor_(TMP, rd, TMP);  // Original rs.
     xor_(ro, rd, rt);
-    and_(ro, ro, TMP1);
+    and_(ro, ro, TMP);
   } else if (rd == rt) {
-    mov(TMP1, rt);  // Preserve rt.
+    mov(TMP, rt);  // Preserve rt.
     addu(rd, rs, rt);  // rt is overwritten.
-    xor_(TMP1, rd, TMP1);  // Original rt.
+    xor_(TMP, rd, TMP);  // Original rt.
     xor_(ro, rd, rs);
-    and_(ro, ro, TMP1);
+    and_(ro, ro, TMP);
   } else {
     addu(rd, rs, rt);
     xor_(ro, rd, rs);
-    xor_(TMP1, rd, rt);
-    and_(ro, TMP1, ro);
+    xor_(TMP, rd, rt);
+    and_(ro, TMP, ro);
   }
 }
 
 
 void Assembler::SubuDetectOverflow(Register rd, Register rs, Register rt,
                                    Register ro) {
   ASSERT(rd != ro);
-  ASSERT(rd != TMP1);
-  ASSERT(ro != TMP1);
+  ASSERT(rd != TMP);
+  ASSERT(ro != TMP);
   ASSERT(ro != rs);
   ASSERT(ro != rt);
-  ASSERT(rs != TMP1);
-  ASSERT(rt != TMP1);
+  ASSERT(rs != TMP);
+  ASSERT(rt != TMP);
 
   // This happens with some crankshaft code. Since Subu works fine if
   // left == right, let's not make that restriction here.
   if (rs == rt) {
     mov(rd, ZR);
     mov(ro, ZR);
     return;
   }
 
   if (rd == rs) {
-    mov(TMP1, rs);  // Preserve left.
+    mov(TMP, rs);  // Preserve left.
     subu(rd, rs, rt);  // Left is overwritten.
-    xor_(ro, rd, TMP1);  // scratch is original left.
-    xor_(TMP1, TMP1, rs);  // scratch is original left.
-    and_(ro, TMP1, ro);
+    xor_(ro, rd, TMP);  // scratch is original left.
+    xor_(TMP, TMP, rs);  // scratch is original left.
+    and_(ro, TMP, ro);
   } else if (rd == rt) {
-    mov(TMP1, rt);  // Preserve right.
+    mov(TMP, rt);  // Preserve right.
     subu(rd, rs, rt);  // Right is overwritten.
     xor_(ro, rd, rs);
-    xor_(TMP1, rs, TMP1);  // Original right.
-    and_(ro, TMP1, ro);
+    xor_(TMP, rs, TMP);  // Original right.
+    and_(ro, TMP, ro);
   } else {
     subu(rd, rs, rt);
     xor_(ro, rd, rs);
-    xor_(TMP1, rs, rt);
-    and_(ro, TMP1, ro);
+    xor_(TMP, rs, rt);
+    and_(ro, TMP, ro);
   }
 }
 
 
 void Assembler::LoadObject(Register rd, const Object& object) {
   // Smis and VM heap objects are never relocated; do not use object pool.
   if (object.IsSmi()) {
     LoadImmediate(rd, reinterpret_cast<int32_t>(object.raw()));
   } else if (object.InVMHeap()) {
     // Make sure that class CallPattern is able to decode this load immediate.
@@ skipping 24 matching lines @@
     if (object_pool_.At(i) == obj.raw()) {
       return i;
     }
   }
   object_pool_.Add(obj, Heap::kOld);
   return object_pool_.Length() - 1;
 }
 
 
 void Assembler::PushObject(const Object& object) {
-  LoadObject(TMP1, object);
-  Push(TMP1);
+  LoadObject(TMP, object);
+  Push(TMP);
 }
 
 
 void Assembler::CompareObject(Register rd1, Register rd2,
                               Register rn, const Object& object) {
-  ASSERT(rn != TMP1);
-  ASSERT(rd1 != TMP1);
+  ASSERT(rn != TMP);
+  ASSERT(rd1 != TMP);
   ASSERT(rd1 != rd2);
-  LoadObject(TMP1, object);
-  slt(rd1, rn, TMP1);
-  slt(rd2, TMP1, rn);
+  LoadObject(TMP, object);
+  slt(rd1, rn, TMP);
+  slt(rd2, TMP, rn);
 }
 
 
 // Preserves object and value registers.
 void Assembler::StoreIntoObjectFilterNoSmi(Register object,
                                            Register value,
                                            Label* no_update) {
   COMPILE_ASSERT((kNewObjectAlignmentOffset == kWordSize) &&
                  (kOldObjectAlignmentOffset == 0), young_alignment);
 
   // Write-barrier triggers if the value is in the new space (has bit set) and
   // the object is in the old space (has bit cleared).
   // To check that, we compute value & ~object and skip the write barrier
   // if the bit is not set. We can't destroy the object.
-  nor(TMP1, ZR, object);
-  and_(TMP1, value, TMP1);
-  andi(CMPRES1, TMP1, Immediate(kNewObjectAlignmentOffset));
+  nor(TMP, ZR, object);
+  and_(TMP, value, TMP);
+  andi(CMPRES1, TMP, Immediate(kNewObjectAlignmentOffset));
   beq(CMPRES1, ZR, no_update);
 }
 
 
 // Preserves object and value registers.
 void Assembler::StoreIntoObjectFilter(Register object,
                                       Register value,
                                       Label* no_update) {
   // For the value we are only interested in the new/old bit and the tag bit.
   // And the new bit with the tag bit. The resulting bit will be 0 for a Smi.
-  sll(TMP1, value, kObjectAlignmentLog2 - 1);
-  and_(TMP1, value, TMP1);
+  sll(TMP, value, kObjectAlignmentLog2 - 1);
+  and_(TMP, value, TMP);
   // And the result with the negated space bit of the object.
   nor(CMPRES1, ZR, object);
-  and_(TMP1, TMP1, CMPRES1);
-  andi(CMPRES1, TMP1, Immediate(kNewObjectAlignmentOffset));
+  and_(TMP, TMP, CMPRES1);
+  andi(CMPRES1, TMP, Immediate(kNewObjectAlignmentOffset));
   beq(CMPRES1, ZR, no_update);
 }
 
 
 void Assembler::StoreIntoObject(Register object,
                                 const Address& dest,
                                 Register value,
                                 bool can_value_be_smi) {
   ASSERT(object != value);
   sw(value, dest);
@@ skipping 41 matching lines @@
   // No store buffer update.
 }
 
 
 void Assembler::StoreIntoObjectNoBarrier(Register object,
                                          const Address& dest,
                                          const Object& value) {
   ASSERT(value.IsSmi() || value.InVMHeap() ||
          (value.IsOld() && value.IsNotTemporaryScopedHandle()));
   // No store buffer update.
-  LoadObject(TMP1, value);
-  sw(TMP1, dest);
+  LoadObject(TMP, value);
+  sw(TMP, dest);
 }
 
 
 void Assembler::LoadClassId(Register result, Register object) {
   ASSERT(RawObject::kClassIdTagBit == 16);
   ASSERT(RawObject::kClassIdTagSize == 16);
   const intptr_t class_id_offset = Object::tags_offset() +
       RawObject::kClassIdTagBit / kBitsPerByte;
   lhu(result, FieldAddress(object, class_id_offset));
 }
 
 
 void Assembler::LoadClassById(Register result, Register class_id) {
   ASSERT(result != class_id);
   lw(result, FieldAddress(CTX, Context::isolate_offset()));
   const intptr_t table_offset_in_isolate =
       Isolate::class_table_offset() + ClassTable::table_offset();
   lw(result, Address(result, table_offset_in_isolate));
-  sll(TMP1, class_id, 2);
-  addu(result, result, TMP1);
+  sll(TMP, class_id, 2);
+  addu(result, result, TMP);
   lw(result, Address(result));
 }
 
 
 void Assembler::LoadClass(Register result, Register object) {
-  ASSERT(TMP1 != result);
-  LoadClassId(TMP1, object);
+  ASSERT(TMP != result);
+  LoadClassId(TMP, object);
 
   lw(result, FieldAddress(CTX, Context::isolate_offset()));
   const intptr_t table_offset_in_isolate =
       Isolate::class_table_offset() + ClassTable::table_offset();
   lw(result, Address(result, table_offset_in_isolate));
-  sll(TMP1, TMP1, 2);
-  addu(result, result, TMP1);
+  sll(TMP, TMP, 2);
+  addu(result, result, TMP);
   lw(result, Address(result));
 }
 
 
 void Assembler::EnterStubFrame(bool uses_pp) {
   SetPrologueOffset();
   if (uses_pp) {
     addiu(SP, SP, Immediate(-4 * kWordSize));
     sw(ZR, Address(SP, 3 * kWordSize));  // PC marker is 0 in stubs.
     sw(RA, Address(SP, 2 * kWordSize));
     sw(FP, Address(SP, 1 * kWordSize));
     sw(PP, Address(SP, 0 * kWordSize));
     addiu(FP, SP, Immediate(1 * kWordSize));
     // Setup pool pointer for this stub.
 
-    GetNextPC(TMP1);  // TMP1 gets the address of the next instruction.
+    GetNextPC(TMP);  // TMP gets the address of the next instruction.
 
     const intptr_t object_pool_pc_dist =
         Instructions::HeaderSize() - Instructions::object_pool_offset() +
         CodeSize();
 
-    lw(PP, Address(TMP1, -object_pool_pc_dist));
+    lw(PP, Address(TMP, -object_pool_pc_dist));
   } else {
     addiu(SP, SP, Immediate(-3 * kWordSize));
     sw(ZR, Address(SP, 2 * kWordSize));  // PC marker is 0 in stubs.
     sw(RA, Address(SP, 1 * kWordSize));
     sw(FP, Address(SP, 0 * kWordSize));
     mov(FP, SP);
   }
 }
 
 
@@ skipping 77 matching lines @@
 void Assembler::EnterDartFrame(intptr_t frame_size) {
   const intptr_t offset = CodeSize();
 
   SetPrologueOffset();
 
   addiu(SP, SP, Immediate(-4 * kWordSize));
   sw(RA, Address(SP, 2 * kWordSize));
   sw(FP, Address(SP, 1 * kWordSize));
   sw(PP, Address(SP, 0 * kWordSize));
 
-  GetNextPC(TMP1);  // TMP1 gets the address of the next instruction.
+  GetNextPC(TMP);  // TMP gets the address of the next instruction.
 
   // Calculate the offset of the pool pointer from the PC.
   const intptr_t object_pool_pc_dist =
       Instructions::HeaderSize() - Instructions::object_pool_offset() +
       CodeSize();
 
   // Save PC in frame for fast identification of corresponding code.
-  AddImmediate(TMP1, -offset);
-  sw(TMP1, Address(SP, 3 * kWordSize));
+  AddImmediate(TMP, -offset);
+  sw(TMP, Address(SP, 3 * kWordSize));
 
   // Set FP to the saved previous FP.
   addiu(FP, SP, Immediate(kWordSize));
 
-  // Load the pool pointer. offset has already been subtracted from TMP1.
-  lw(PP, Address(TMP1, -object_pool_pc_dist + offset));
+  // Load the pool pointer. offset has already been subtracted from TMP.
+  lw(PP, Address(TMP, -object_pool_pc_dist + offset));
 
   // Reserve space for locals.
   AddImmediate(SP, -frame_size);
 }
 
 
 // On entry to a function compiled for OSR, the caller's frame pointer, the
 // stack locals, and any copied parameters are already in place.  The frame
 // pointer is already set up.  The PC marker is not correct for the
 // optimized function and there may be extra space for spill slots to
@@ skipping 50 matching lines @@
   Ret();
   delay_slot()->addiu(SP, SP, Immediate(4 * kWordSize));
 }
 
 
 void Assembler::ReserveAlignedFrameSpace(intptr_t frame_space) {
   // Reserve space for arguments and align frame before entering
   // the C++ world.
   AddImmediate(SP, -frame_space);
   if (OS::ActivationFrameAlignment() > 1) {
-    LoadImmediate(TMP1, ~(OS::ActivationFrameAlignment() - 1));
-    and_(SP, SP, TMP1);
+    LoadImmediate(TMP, ~(OS::ActivationFrameAlignment() - 1));
+    and_(SP, SP, TMP);
   }
 }
 
 
 void Assembler::EnterCallRuntimeFrame(intptr_t frame_space) {
   const intptr_t kPushedRegistersSize =
       kDartVolatileCpuRegCount * kWordSize +
       2 * kWordSize +  // FP and RA.
       kDartVolatileFpuRegCount * kWordSize;
 
@@ skipping 132 matching lines @@
     Bind(&msg);
     break_(Instr::kMsgMessageCode);
   }
 #endif
 }
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_MIPS