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Issue 595093002: Handle "inplace" ops and unary ops w/ assembler (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: format Created 6 years, 2 months ago
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1 ; This checks support for insertelement and extractelement. 1 ; This checks support for insertelement and extractelement.
2 2
3 ; RUN: %llvm2ice -O2 --verbose none %s \ 3 ; RUN: %llvm2ice -O2 --verbose none %s \
4 ; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \ 4 ; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \
5 ; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s 5 ; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
6 ; RUN: %llvm2ice -Om1 --verbose none %s \ 6 ; RUN: %llvm2ice -Om1 --verbose none %s \
7 ; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \ 7 ; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \
8 ; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s 8 ; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
9 ; RUN: %llvm2ice -O2 -mattr=sse4.1 --verbose none %s \ 9 ; RUN: %llvm2ice -O2 -mattr=sse4.1 --verbose none %s \
10 ; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \ 10 ; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \
(...skipping 19 matching lines...) Expand all
30 30
31 ; SSE41-LABEL: insertelement_v4f32_0: 31 ; SSE41-LABEL: insertelement_v4f32_0:
32 ; SSE41: insertps {{.*}}, {{.*}}, 0 32 ; SSE41: insertps {{.*}}, {{.*}}, 0
33 } 33 }
34 34
35 define <4 x i32> @insertelement_v4i32_0(<4 x i32> %vec, i32 %elt) { 35 define <4 x i32> @insertelement_v4i32_0(<4 x i32> %vec, i32 %elt) {
36 entry: 36 entry:
37 %res = insertelement <4 x i32> %vec, i32 %elt, i32 0 37 %res = insertelement <4 x i32> %vec, i32 %elt, i32 0
38 ret <4 x i32> %res 38 ret <4 x i32> %res
39 ; CHECK-LABEL: insertelement_v4i32_0: 39 ; CHECK-LABEL: insertelement_v4i32_0:
40 ; CHECK: movd xmm{{.*}},
40 ; CHECK: movss 41 ; CHECK: movss
41 42
42 ; SSE41-LABEL: insertelement_v4i32_0: 43 ; SSE41-LABEL: insertelement_v4i32_0:
43 ; SSE41: pinsrd {{.*}}, {{.*}}, 0 44 ; SSE41: pinsrd {{.*}}, {{.*}}, 0
44 } 45 }
45 46
46 47
47 define <4 x float> @insertelement_v4f32_1(<4 x float> %vec, float %elt) { 48 define <4 x float> @insertelement_v4f32_1(<4 x float> %vec, float %elt) {
48 entry: 49 entry:
49 %res = insertelement <4 x float> %vec, float %elt, i32 1 50 %res = insertelement <4 x float> %vec, float %elt, i32 1
(...skipping 107 matching lines...) Expand 10 before | Expand all | Expand 10 after
157 ; SSE41-LABEL: extractelement_v4f32: 158 ; SSE41-LABEL: extractelement_v4f32:
158 ; SSE41: pshufd 159 ; SSE41: pshufd
159 } 160 }
160 161
161 define i32 @extractelement_v4i32(<4 x i32> %vec) { 162 define i32 @extractelement_v4i32(<4 x i32> %vec) {
162 entry: 163 entry:
163 %res = extractelement <4 x i32> %vec, i32 1 164 %res = extractelement <4 x i32> %vec, i32 1
164 ret i32 %res 165 ret i32 %res
165 ; CHECK-LABEL: extractelement_v4i32: 166 ; CHECK-LABEL: extractelement_v4i32:
166 ; CHECK: pshufd 167 ; CHECK: pshufd
168 ; CHECK: movd {{.*}}, xmm
167 169
168 ; SSE41-LABEL: extractelement_v4i32: 170 ; SSE41-LABEL: extractelement_v4i32:
169 ; SSE41: pextrd 171 ; SSE41: pextrd
170 } 172 }
171 173
172 define i32 @extractelement_v8i16(<8 x i16> %vec) { 174 define i32 @extractelement_v8i16(<8 x i16> %vec) {
173 entry: 175 entry:
174 %res = extractelement <8 x i16> %vec, i32 1 176 %res = extractelement <8 x i16> %vec, i32 1
175 %res.ext = zext i16 %res to i32 177 %res.ext = zext i16 %res to i32
176 ret i32 %res.ext 178 ret i32 %res.ext
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228 ; CHECK: movups 230 ; CHECK: movups
229 ; CHECK: lea 231 ; CHECK: lea
230 ; CHECK: mov 232 ; CHECK: mov
231 233
232 ; SSE41-LABEL: extractelement_v16i1: 234 ; SSE41-LABEL: extractelement_v16i1:
233 ; SSE41: pextrb 235 ; SSE41: pextrb
234 } 236 }
235 237
236 ; ERRORS-NOT: ICE translation error 238 ; ERRORS-NOT: ICE translation error
237 ; DUMP-NOT: SZ 239 ; DUMP-NOT: SZ
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