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Issue 595023: ARM optimize loading of immediates. (Closed)
Patch Set: Created 10 years, 10 months ago
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1 // Copyright 2010 the V8 project authors. All rights reserved. 1 // Copyright 2010 the V8 project authors. All rights reserved.
2 // Redistribution and use in source and binary forms, with or without 2 // Redistribution and use in source and binary forms, with or without
3 // modification, are permitted provided that the following conditions are 3 // modification, are permitted provided that the following conditions are
4 // met: 4 // met:
5 // 5 //
6 // * Redistributions of source code must retain the above copyright 6 // * Redistributions of source code must retain the above copyright
7 // notice, this list of conditions and the following disclaimer. 7 // notice, this list of conditions and the following disclaimer.
8 // * Redistributions in binary form must reproduce the above 8 // * Redistributions in binary form must reproduce the above
9 // copyright notice, this list of conditions and the following 9 // copyright notice, this list of conditions and the following
10 // disclaimer in the documentation and/or other materials provided 10 // disclaimer in the documentation and/or other materials provided
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932 932
933 // Addressing Mode 1 - Data-processing operands: 933 // Addressing Mode 1 - Data-processing operands:
934 // Get the value based on the shifter_operand with register. 934 // Get the value based on the shifter_operand with register.
935 int32_t Simulator::GetShiftRm(Instr* instr, bool* carry_out) { 935 int32_t Simulator::GetShiftRm(Instr* instr, bool* carry_out) {
936 Shift shift = instr->ShiftField(); 936 Shift shift = instr->ShiftField();
937 int shift_amount = instr->ShiftAmountField(); 937 int shift_amount = instr->ShiftAmountField();
938 int32_t result = get_register(instr->RmField()); 938 int32_t result = get_register(instr->RmField());
939 if (instr->Bit(4) == 0) { 939 if (instr->Bit(4) == 0) {
940 // by immediate 940 // by immediate
941 if ((shift == ROR) && (shift_amount == 0)) { 941 if ((shift == ROR) && (shift_amount == 0)) {
942 // RRX.
942 UNIMPLEMENTED(); 943 UNIMPLEMENTED();
943 return result; 944 return result;
944 } else if (((shift == LSR) || (shift == ASR)) && (shift_amount == 0)) { 945 } else if (((shift == LSR) || (shift == ASR)) && (shift_amount == 0)) {
945 shift_amount = 32; 946 shift_amount = 32;
946 } 947 }
947 switch (shift) { 948 switch (shift) {
948 case ASR: { 949 case ASR: {
949 if (shift_amount == 0) { 950 if (shift_amount == 0) {
950 if (result < 0) { 951 if (result < 0) {
951 result = 0xffffffff; 952 result = 0xffffffff;
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981 uint32_t uresult = static_cast<uint32_t>(result); 982 uint32_t uresult = static_cast<uint32_t>(result);
982 uresult >>= (shift_amount - 1); 983 uresult >>= (shift_amount - 1);
983 *carry_out = (uresult & 1) == 1; 984 *carry_out = (uresult & 1) == 1;
984 uresult >>= 1; 985 uresult >>= 1;
985 result = static_cast<int32_t>(uresult); 986 result = static_cast<int32_t>(uresult);
986 } 987 }
987 break; 988 break;
988 } 989 }
989 990
990 case ROR: { 991 case ROR: {
991 UNIMPLEMENTED(); 992 uint32_t uresult = static_cast<uint32_t>(result);
993 uresult =
994 (uresult >> shift_amount) | (uresult << (32 - shift_amount));
995 *carry_out = (uresult >> 31) != 0;
996 result = static_cast<int32_t>(uresult);
992 break; 997 break;
993 } 998 }
994 999
995 default: { 1000 default: {
996 UNREACHABLE(); 1001 UNREACHABLE();
997 break; 1002 break;
998 } 1003 }
999 } 1004 }
1000 } else { 1005 } else {
1001 // by register 1006 // by register
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2303 uintptr_t* stack_slot = reinterpret_cast<uintptr_t*>(current_sp); 2308 uintptr_t* stack_slot = reinterpret_cast<uintptr_t*>(current_sp);
2304 uintptr_t address = *stack_slot; 2309 uintptr_t address = *stack_slot;
2305 set_register(sp, current_sp + sizeof(uintptr_t)); 2310 set_register(sp, current_sp + sizeof(uintptr_t));
2306 return address; 2311 return address;
2307 } 2312 }
2308 2313
2309 2314
2310 } } // namespace assembler::arm 2315 } } // namespace assembler::arm
2311 2316
2312 #endif // !defined(__arm__) 2317 #endif // !defined(__arm__)
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