Expands the use of Immediate and Operand wrappers.

runtime/vm/assembler_arm.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/globals.h"
 #if defined(TARGET_ARCH_ARM)
 
 #include "vm/assembler.h"
 #include "vm/cpu.h"
 #include "vm/longjump.h"
@@ skipping 2230 matching lines @@
 }
 
 
 void Assembler::MoveRegister(Register rd, Register rm, Condition cond) {
   if (rd != rm) {
     mov(rd, Operand(rm), cond);
   }
 }
 
 
-void Assembler::Lsl(Register rd, Register rm, uint32_t shift_imm,
+void Assembler::Lsl(Register rd, Register rm, const Operand& shift_imm,
                     Condition cond) {
-  ASSERT(shift_imm != 0);  // Do not use Lsl if no shift is wanted.
-  mov(rd, Operand(rm, LSL, shift_imm), cond);
+  ASSERT(shift_imm.type() == 1);
+  ASSERT(shift_imm.encoding() != 0);  // Do not use Lsl if no shift is wanted.
+  mov(rd, Operand(rm, LSL, shift_imm.encoding()), cond);
 }
 
 
 void Assembler::Lsl(Register rd, Register rm, Register rs, Condition cond) {
   mov(rd, Operand(rm, LSL, rs), cond);
 }
 
 
-void Assembler::Lsr(Register rd, Register rm, uint32_t shift_imm,
+void Assembler::Lsr(Register rd, Register rm, const Operand& shift_imm,
                     Condition cond) {
-  ASSERT(shift_imm != 0);  // Do not use Lsr if no shift is wanted.
-  if (shift_imm == 32) shift_imm = 0;  // Comply to UAL syntax.
-  mov(rd, Operand(rm, LSR, shift_imm), cond);
+  ASSERT(shift_imm.type() == 1);
+  uint32_t shift = shift_imm.encoding();
+  ASSERT(shift != 0);  // Do not use Lsr if no shift is wanted.
+  if (shift == 32) {
+    shift = 0;  // Comply to UAL syntax.
+  }
+  mov(rd, Operand(rm, LSR, shift), cond);
 }
 
 
 void Assembler::Lsr(Register rd, Register rm, Register rs, Condition cond) {
   mov(rd, Operand(rm, LSR, rs), cond);
 }
 
 
-void Assembler::Asr(Register rd, Register rm, uint32_t shift_imm,
+void Assembler::Asr(Register rd, Register rm, const Operand& shift_imm,
                     Condition cond) {
-  ASSERT(shift_imm != 0);  // Do not use Asr if no shift is wanted.
-  if (shift_imm == 32) {
-    shift_imm = 0;  // Comply to UAL syntax.
+  ASSERT(shift_imm.type() == 1);
+  uint32_t shift = shift_imm.encoding();
+  ASSERT(shift != 0);  // Do not use Asr if no shift is wanted.
+  if (shift == 32) {
+    shift = 0;  // Comply to UAL syntax.
   }
-  mov(rd, Operand(rm, ASR, shift_imm), cond);
+  mov(rd, Operand(rm, ASR, shift), cond);
 }
 
 
-void Assembler::Asrs(Register rd, Register rm, uint32_t shift_imm,
+void Assembler::Asrs(Register rd, Register rm, const Operand& shift_imm,
                      Condition cond) {
-  ASSERT(shift_imm != 0);  // Do not use Asr if no shift is wanted.
-  if (shift_imm == 32) {
-    shift_imm = 0;  // Comply to UAL syntax.
+  ASSERT(shift_imm.type() == 1);
+  uint32_t shift = shift_imm.encoding();
+  ASSERT(shift != 0);  // Do not use Asr if no shift is wanted.
+  if (shift == 32) {
+    shift = 0;  // Comply to UAL syntax.
   }
-  movs(rd, Operand(rm, ASR, shift_imm), cond);
+  movs(rd, Operand(rm, ASR, shift), cond);
 }
 
 
 void Assembler::Asr(Register rd, Register rm, Register rs, Condition cond) {
   mov(rd, Operand(rm, ASR, rs), cond);
 }
 
 
-void Assembler::Ror(Register rd, Register rm, uint32_t shift_imm,
+void Assembler::Ror(Register rd, Register rm, const Operand& shift_imm,
                     Condition cond) {
-  ASSERT(shift_imm != 0);  // Use Rrx instruction.
-  mov(rd, Operand(rm, ROR, shift_imm), cond);
+  ASSERT(shift_imm.type() == 1);
+  ASSERT(shift_imm.encoding() != 0);  // Use Rrx instruction.
+  mov(rd, Operand(rm, ROR, shift_imm.encoding()), cond);
 }
 
 
 void Assembler::Ror(Register rd, Register rm, Register rs, Condition cond) {
   mov(rd, Operand(rm, ROR, rs), cond);
 }
 
 
 void Assembler::Rrx(Register rd, Register rm, Condition cond) {
   mov(rd, Operand(rm, ROR, 0), cond);
 }
 
 
 void Assembler::SignFill(Register rd, Register rm, Condition cond) {
-  Asr(rd, rm, 31, cond);
+  Asr(rd, rm, Operand(31), cond);
 }
 
 
 void Assembler::Vreciprocalqs(QRegister qd, QRegister qm) {
   ASSERT(qm != QTMP);
   ASSERT(qd != QTMP);
 
   // Reciprocal estimate.
   vrecpeqs(qd, qm);
   // 2 Newton-Raphson steps.
@@ skipping 1069 matching lines @@
 
 
 const char* Assembler::FpuRegisterName(FpuRegister reg) {
   ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters));
   return fpu_reg_names[reg];
 }
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_ARM