Expands the use of Immediate and Operand wrappers.

runtime/vm/assembler_mips.h

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #ifndef VM_ASSEMBLER_MIPS_H_
 #define VM_ASSEMBLER_MIPS_H_
 
 #ifndef VM_ASSEMBLER_H_
 #error Do not include assembler_mips.h directly; use assembler.h instead.
 #endif
@@ skipping 32 matching lines @@
 
   friend class Assembler;
 };
 
 
 class Address : public ValueObject {
  public:
   explicit Address(Register base, int32_t offset = 0)
       : ValueObject(), base_(base), offset_(offset) { }
 
+  // This addressing mode does not exist.
+  Address(Register base, Register offset);
+
   Address(const Address& other)
       : ValueObject(), base_(other.base_), offset_(other.offset_) { }
   Address& operator=(const Address& other) {
     base_ = other.base_;
     offset_ = other.offset_;
     return *this;
   }
 
   uint32_t encoding() const {
     ASSERT(Utils::IsInt(kImmBits, offset_));
@@ skipping 862 matching lines @@
     } else {
       LoadImmediate(TMP, imm);
       and_(rd, rs, TMP);
     }
   }
 
   void BranchEqual(Register rd, Register rn, Label* l) {
     beq(rd, rn, l);
   }
 
-  void BranchEqual(Register rd, int32_t value, Label* l) {
+  void BranchEqual(Register rd, const Immediate& imm, Label* l) {
     ASSERT(!in_delay_slot_);
-    if (value == 0) {
+    if (imm.value() == 0) {
       beq(rd, ZR, l);
     } else {
       ASSERT(rd != CMPRES2);
-      LoadImmediate(CMPRES2, value);
+      LoadImmediate(CMPRES2, imm.value());
       beq(rd, CMPRES2, l);
     }
   }
 
   void BranchEqual(Register rd, const Object& object, Label* l) {
     ASSERT(!in_delay_slot_);
     ASSERT(rd != CMPRES2);
     LoadObject(CMPRES2, object);
     beq(rd, CMPRES2, l);
   }
 
   void BranchNotEqual(Register rd, Register rn, Label* l) {
     bne(rd, rn, l);
   }
 
-  void BranchNotEqual(Register rd, int32_t value, Label* l) {
+  void BranchNotEqual(Register rd, const Immediate& imm, Label* l) {
     ASSERT(!in_delay_slot_);
-    if (value == 0) {
+    if (imm.value() == 0) {
       bne(rd, ZR, l);
     } else {
       ASSERT(rd != CMPRES2);
-      LoadImmediate(CMPRES2, value);
+      LoadImmediate(CMPRES2, imm.value());
       bne(rd, CMPRES2, l);
     }
   }
 
   void BranchNotEqual(Register rd, const Object& object, Label* l) {
     ASSERT(!in_delay_slot_);
     ASSERT(rd != CMPRES2);
     LoadObject(CMPRES2, object);
     bne(rd, CMPRES2, l);
   }
 
   void BranchSignedGreater(Register rd, Register rs, Label* l) {
     ASSERT(!in_delay_slot_);
     slt(CMPRES2, rs, rd);  // CMPRES2 = rd > rs ? 1 : 0.
     bne(CMPRES2, ZR, l);
   }
 
-  void BranchSignedGreater(Register rd, int32_t value, Label* l) {
+  void BranchSignedGreater(Register rd, const Immediate& imm, Label* l) {
     ASSERT(!in_delay_slot_);
-    if (value == 0) {
+    if (imm.value() == 0) {
       bgtz(rd, l);
     } else {
       ASSERT(rd != CMPRES2);
-      LoadImmediate(CMPRES2, value);
+      LoadImmediate(CMPRES2, imm.value());
       BranchSignedGreater(rd, CMPRES2, l);
     }
   }
 
   void BranchUnsignedGreater(Register rd, Register rs, Label* l) {
     ASSERT(!in_delay_slot_);
     sltu(CMPRES2, rs, rd);
     bne(CMPRES2, ZR, l);
   }
 
-  void BranchUnsignedGreater(Register rd, int32_t value, Label* l) {
+  void BranchUnsignedGreater(Register rd, const Immediate& imm, Label* l) {
     ASSERT(!in_delay_slot_);
-    if (value == 0) {
-      BranchNotEqual(rd, 0, l);
+    if (imm.value() == 0) {
+      BranchNotEqual(rd, Immediate(0), l);
     } else {
       ASSERT(rd != CMPRES2);
-      LoadImmediate(CMPRES2, value);
+      LoadImmediate(CMPRES2, imm.value());
       BranchUnsignedGreater(rd, CMPRES2, l);
     }
   }
 
   void BranchSignedGreaterEqual(Register rd, Register rs, Label* l) {
     ASSERT(!in_delay_slot_);
     slt(CMPRES2, rd, rs);  // CMPRES2 = rd < rs ? 1 : 0.
     beq(CMPRES2, ZR, l);  // If CMPRES2 = 0, then rd >= rs.
   }
 
-  void BranchSignedGreaterEqual(Register rd, int32_t value, Label* l) {
+  void BranchSignedGreaterEqual(Register rd, const Immediate& imm, Label* l) {
     ASSERT(!in_delay_slot_);
-    if (value == 0) {
+    if (imm.value() == 0) {
       bgez(rd, l);
     } else {
-      if (Utils::IsInt(kImmBits, value)) {
-        slti(CMPRES2, rd, Immediate(value));
+      if (Utils::IsInt(kImmBits, imm.value())) {
+        slti(CMPRES2, rd, imm);
         beq(CMPRES2, ZR, l);
       } else {
         ASSERT(rd != CMPRES2);
-        LoadImmediate(CMPRES2, value);
+        LoadImmediate(CMPRES2, imm.value());
         BranchSignedGreaterEqual(rd, CMPRES2, l);
       }
     }
   }
 
   void BranchUnsignedGreaterEqual(Register rd, Register rs, Label* l) {
     ASSERT(!in_delay_slot_);
     sltu(CMPRES2, rd, rs);  // CMPRES2 = rd < rs ? 1 : 0.
     beq(CMPRES2, ZR, l);
   }
 
-  void BranchUnsignedGreaterEqual(Register rd, int32_t value, Label* l) {
+  void BranchUnsignedGreaterEqual(Register rd, const Immediate& imm, Label* l) {
     ASSERT(!in_delay_slot_);
-    if (value == 0) {
+    if (imm.value() == 0) {
       b(l);
     } else {
-      if (Utils::IsUint(kImmBits, value)) {
-        sltiu(CMPRES2, rd, Immediate(value));
+      if (Utils::IsUint(kImmBits, imm.value())) {
+        sltiu(CMPRES2, rd, imm);
         beq(CMPRES2, ZR, l);
       } else {
         ASSERT(rd != CMPRES2);
-        LoadImmediate(CMPRES2, value);
+        LoadImmediate(CMPRES2, imm.value());
         BranchUnsignedGreaterEqual(rd, CMPRES2, l);
       }
     }
   }
 
   void BranchSignedLess(Register rd, Register rs, Label* l) {
     ASSERT(!in_delay_slot_);
     BranchSignedGreater(rs, rd, l);
   }
 
-  void BranchSignedLess(Register rd, int32_t value, Label* l) {
+  void BranchSignedLess(Register rd, const Immediate& imm, Label* l) {
     ASSERT(!in_delay_slot_);
-    if (value == 0) {
+    if (imm.value() == 0) {
       bltz(rd, l);
     } else {
-      if (Utils::IsInt(kImmBits, value)) {
-        slti(CMPRES2, rd, Immediate(value));
+      if (Utils::IsInt(kImmBits, imm.value())) {
+        slti(CMPRES2, rd, imm);
         bne(CMPRES2, ZR, l);
       } else {
         ASSERT(rd != CMPRES2);
-        LoadImmediate(CMPRES2, value);
+        LoadImmediate(CMPRES2, imm.value());
         BranchSignedGreater(CMPRES2, rd, l);
       }
     }
   }
 
   void BranchUnsignedLess(Register rd, Register rs, Label* l) {
     ASSERT(!in_delay_slot_);
     BranchUnsignedGreater(rs, rd, l);
   }
 
-  void BranchUnsignedLess(Register rd, int32_t value, Label* l) {
+  void BranchUnsignedLess(Register rd, const Immediate& imm, Label* l) {
     ASSERT(!in_delay_slot_);
-    ASSERT(value != 0);
-    if (Utils::IsUint(kImmBits, value)) {
-      sltiu(CMPRES2, rd, Immediate(value));
+    ASSERT(imm.value() != 0);
+    if (Utils::IsUint(kImmBits, imm.value())) {
+      sltiu(CMPRES2, rd, imm);
       bne(CMPRES2, ZR, l);
     } else {
       ASSERT(rd != CMPRES2);
-      LoadImmediate(CMPRES2, value);
+      LoadImmediate(CMPRES2, imm.value());
       BranchUnsignedGreater(CMPRES2, rd, l);
     }
   }
 
   void BranchSignedLessEqual(Register rd, Register rs, Label* l) {
     ASSERT(!in_delay_slot_);
     BranchSignedGreaterEqual(rs, rd, l);
   }
 
-  void BranchSignedLessEqual(Register rd, int32_t value, Label* l) {
+  void BranchSignedLessEqual(Register rd, const Immediate& imm, Label* l) {
     ASSERT(!in_delay_slot_);
-    if (value == 0) {
+    if (imm.value() == 0) {
       blez(rd, l);
     } else {
       ASSERT(rd != CMPRES2);
-      LoadImmediate(CMPRES2, value);
+      LoadImmediate(CMPRES2, imm.value());
       BranchSignedGreaterEqual(CMPRES2, rd, l);
     }
   }
 
   void BranchUnsignedLessEqual(Register rd, Register rs, Label* l) {
     ASSERT(!in_delay_slot_);
     BranchUnsignedGreaterEqual(rs, rd, l);
   }
 
-  void BranchUnsignedLessEqual(Register rd, int32_t value, Label* l) {
+  void BranchUnsignedLessEqual(Register rd, const Immediate& imm, Label* l) {
     ASSERT(!in_delay_slot_);
     ASSERT(rd != CMPRES2);
-    LoadImmediate(CMPRES2, value);
+    LoadImmediate(CMPRES2, imm.value());
     BranchUnsignedGreaterEqual(CMPRES2, rd, l);
   }
 
   void Push(Register rt) {
     ASSERT(!in_delay_slot_);
     addiu(SP, SP, Immediate(-kWordSize));
     sw(rt, Address(SP));
   }
 
   void Pop(Register rt) {
@@ skipping 277 matching lines @@
                                   Register value,
                                   Label* no_update);
 
   DISALLOW_ALLOCATION();
   DISALLOW_COPY_AND_ASSIGN(Assembler);
 };
 
 }  // namespace dart
 
 #endif  // VM_ASSEMBLER_MIPS_H_