Expands the use of Immediate and Operand wrappers.

runtime/vm/assembler_arm64.h

 // Copyright (c) 2014, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #ifndef VM_ASSEMBLER_ARM64_H_
 #define VM_ASSEMBLER_ARM64_H_
 
 #ifndef VM_ASSEMBLER_H_
 #error Do not include assembler_arm64.h directly; use assembler.h instead.
 #endif
 
 #include "platform/assert.h"
 #include "platform/utils.h"
 #include "vm/constants_arm64.h"
 #include "vm/hash_map.h"
 #include "vm/longjump.h"
 #include "vm/object.h"
 #include "vm/simulator.h"
 
 namespace dart {
 
 // Forward declarations.
 class RuntimeEntry;
 
+class Immediate : public ValueObject {
+ public:
+  explicit Immediate(int64_t value) : value_(value) { }
+
+  Immediate(const Immediate& other) : ValueObject(), value_(other.value_) { }
+  Immediate& operator=(const Immediate& other) {
+    value_ = other.value_;
+    return *this;
+  }
+
+ private:
+  int64_t value_;
+
+  int64_t value() const { return value_; }
+
+  friend class Assembler;
+};
+
+
 class Label : public ValueObject {
  public:
   Label() : position_(0) { }
 
   ~Label() {
     // Assert if label is being destroyed with unresolved branches pending.
     ASSERT(!IsLinked());
   }
 
   // Returns the position for bound and linked labels. Cannot be used
@@ skipping 84 matching lines @@
       int32_t idx = (at == PostIndex) ? B10 : (B11 | B10);
       encoding_ =
           idx |
           ((offset & 0x1ff) << kImm9Shift) |
           (static_cast<int32_t>(crn) << kRnShift);
     }
     type_ = at;
     base_ = crn;
   }
 
+  // This addressing mode does not exist.
+  Address(Register rn, Register offset, AddressType at,
+          OperandSize sz = kDoubleWord);
+
   static bool CanHoldOffset(int32_t offset, AddressType at = Offset,
                             OperandSize sz = kDoubleWord) {
     if (at == Offset) {
       // Offset fits in 12 bit unsigned and has right alignment for sz,
       // or fits in 9 bit signed offset with no alignment restriction.
       const int32_t scale = Log2OperandSizeBytes(sz);
       return (Utils::IsUint(12 + scale, offset) &&
               (offset == ((offset >> scale) << scale))) ||
              (Utils::IsInt(9, offset));
     } else if (at == PCOffset) {
       return Utils::IsInt(21, offset) &&
              (offset == ((offset >> 2) << 2));
     } else {
       ASSERT((at == PreIndex) || (at == PostIndex));
       return Utils::IsInt(9, offset);
     }
   }
 
   // PC-relative load address.
   static Address PC(int32_t pc_off) {
     ASSERT(CanHoldOffset(pc_off, PCOffset));
     Address addr;
     addr.encoding_ = (((pc_off >> 2) << kImm19Shift) & kImm19Mask);
     addr.base_ = kNoRegister;
     addr.type_ = PCOffset;
     return addr;
   }
 
+  // This addressing mode does not exist.
+  static Address PC(Register r);
+
   enum Scaling {
     Unscaled,
     Scaled,
   };
 
   // Base register rn with offset rm. rm is sign-extended according to ext.
   // If ext is UXTX, rm may be optionally scaled by the
   // Log2OperandSize (specified by the instruction).
   Address(Register rn, Register rm,
           Extend ext = UXTX, Scaling scale = Unscaled) {
@@ skipping 72 matching lines @@
 
   friend class Assembler;
 };
 
 
 class FieldAddress : public Address {
  public:
   FieldAddress(Register base, int32_t disp, OperandSize sz = kDoubleWord)
       : Address(base, disp - kHeapObjectTag, Offset, sz) { }
 
+  // This addressing mode does not exist.
+  FieldAddress(Register base, Register disp, OperandSize sz = kDoubleWord)
+      : Address(base) {
+    UNREACHABLE();
+  }
+
   FieldAddress(const FieldAddress& other) : Address(other) { }
 
   FieldAddress& operator=(const FieldAddress& other) {
     Address::operator=(other);
     return *this;
   }
 };
 
 
 class Operand : public ValueObject {
@@ skipping 30 matching lines @@
     ASSERT(Utils::IsUint(6, imm));
     ASSERT((rm != R31) && (rm != CSP));
     const Register crm = ConcreteRegister(rm);
     encoding_ =
         (imm << kImm6Shift) |
         (static_cast<int32_t>(crm) << kRmShift) |
         (static_cast<int32_t>(shift) << kShiftTypeShift);
     type_ = Shifted;
   }
 
+  // This operand type does not exist.
+  Operand(Register rm, Shift shift, Register r);
+
   Operand(Register rm, Extend extend, int32_t imm) {
     ASSERT(Utils::IsUint(3, imm));
     ASSERT((rm != R31) && (rm != CSP));
     const Register crm = ConcreteRegister(rm);
     encoding_ =
         B21 |
         (static_cast<int32_t>(crm) << kRmShift) |
         (static_cast<int32_t>(extend) << kExtendTypeShift) |
         ((imm & 0x7) << kImm3Shift);
     type_ = Extended;
   }
 
+  // This operand type does not exist.
+  Operand(Register rm, Extend extend, Register r);
+
   explicit Operand(int32_t imm) {
     if (Utils::IsUint(12, imm)) {
       encoding_ = imm << kImm12Shift;
     } else {
       // imm only has bits in [12, 24) set.
       ASSERT(((imm & 0xfff) == 0) && (Utils::IsUint(12, imm >> 12)));
       encoding_ = B22 | ((imm >> 12) << kImm12Shift);
     }
     type_ = Immediate;
   }
@@ skipping 120 matching lines @@
   static const char* FpuRegisterName(FpuRegister reg);
 
   void SetPrologueOffset() {
     if (prologue_offset_ == -1) {
       prologue_offset_ = CodeSize();
     }
   }
 
   void ReserveAlignedFrameSpace(intptr_t frame_space);
 
-  // TODO(zra): Make sure this is right.
   // Instruction pattern from entrypoint is used in Dart frame prologs
   // to set up the frame and save a PC which can be used to figure out the
   // RawInstruction object corresponding to the code running in the frame.
   static const intptr_t kEntryPointToPcMarkerOffset = 0;
   static intptr_t EntryPointToPcMarkerOffset() {
     return kEntryPointToPcMarkerOffset;
   }
 
   // Emit data (e.g encoded instruction or immediate) in instruction stream.
   void Emit(int32_t value);
@@ skipping 16 matching lines @@
     AddSubHelper(kWord, false, false, rd, rn, o);
   }
   void sub(Register rd, Register rn, Operand o) {
     AddSubHelper(kDoubleWord, false, true, rd, rn, o);
   }
   void subs(Register rd, Register rn, Operand o) {
     AddSubHelper(kDoubleWord, true, true, rd, rn, o);
   }
 
   // PC relative immediate add. imm is in bytes.
-  void adr(Register rd, int64_t imm) {
+  void adr(Register rd, const Immediate& imm) {
     EmitPCRelOp(ADR, rd, imm);
   }
 
   // Logical immediate operations.
-  void andi(Register rd, Register rn, uint64_t imm) {
+  void andi(Register rd, Register rn, const Immediate& imm) {
     Operand imm_op;
-    const bool immok = Operand::IsImmLogical(imm, kXRegSizeInBits, &imm_op);
+    const bool immok =
+        Operand::IsImmLogical(imm.value(), kXRegSizeInBits, &imm_op);
     ASSERT(immok);
     EmitLogicalImmOp(ANDI, rd, rn, imm_op, kDoubleWord);
   }
-  void orri(Register rd, Register rn, uint64_t imm) {
+  void orri(Register rd, Register rn, const Immediate& imm) {
     Operand imm_op;
-    const bool immok = Operand::IsImmLogical(imm, kXRegSizeInBits, &imm_op);
+    const bool immok =
+        Operand::IsImmLogical(imm.value(), kXRegSizeInBits, &imm_op);
     ASSERT(immok);
     EmitLogicalImmOp(ORRI, rd, rn, imm_op, kDoubleWord);
   }
-  void eori(Register rd, Register rn, uint64_t imm) {
+  void eori(Register rd, Register rn, const Immediate& imm) {
     Operand imm_op;
-    const bool immok = Operand::IsImmLogical(imm, kXRegSizeInBits, &imm_op);
+    const bool immok =
+        Operand::IsImmLogical(imm.value(), kXRegSizeInBits, &imm_op);
     ASSERT(immok);
     EmitLogicalImmOp(EORI, rd, rn, imm_op, kDoubleWord);
   }
-  void andis(Register rd, Register rn, uint64_t imm) {
+  void andis(Register rd, Register rn, const Immediate& imm) {
     Operand imm_op;
-    const bool immok = Operand::IsImmLogical(imm, kXRegSizeInBits, &imm_op);
+    const bool immok =
+        Operand::IsImmLogical(imm.value(), kXRegSizeInBits, &imm_op);
     ASSERT(immok);
     EmitLogicalImmOp(ANDIS, rd, rn, imm_op, kDoubleWord);
   }
 
   // Logical (shifted) register operations.
   void and_(Register rd, Register rn, Operand o) {
     EmitLogicalShiftOp(AND, rd, rn, o, kDoubleWord);
   }
   void andw_(Register rd, Register rn, Operand o) {
     EmitLogicalShiftOp(AND, rd, rn, o, kWord);
@@ skipping 43 matching lines @@
     EmitMiscDP3Source(MADD, rd, rn, rm, ra, kDoubleWord);
   }
   void msub(Register rd, Register rn, Register rm, Register ra) {
     EmitMiscDP3Source(MSUB, rd, rn, rm, ra, kDoubleWord);
   }
   void smulh(Register rd, Register rn, Register rm) {
     EmitMiscDP3Source(SMULH, rd, rn, rm, R0, kDoubleWord);
   }
 
   // Move wide immediate.
-  void movk(Register rd, uint16_t imm, int hw_idx) {
+  void movk(Register rd, const Immediate& imm, int hw_idx) {
     ASSERT(rd != CSP);
     const Register crd = ConcreteRegister(rd);
     EmitMoveWideOp(MOVK, crd, imm, hw_idx, kDoubleWord);
   }
-  void movn(Register rd, uint16_t imm, int hw_idx) {
+  void movn(Register rd, const Immediate& imm, int hw_idx) {
     ASSERT(rd != CSP);
     const Register crd = ConcreteRegister(rd);
     EmitMoveWideOp(MOVN, crd, imm, hw_idx, kDoubleWord);
   }
-  void movz(Register rd, uint16_t imm, int hw_idx) {
+  void movz(Register rd, const Immediate& imm, int hw_idx) {
     ASSERT(rd != CSP);
     const Register crd = ConcreteRegister(rd);
     EmitMoveWideOp(MOVZ, crd, imm, hw_idx, kDoubleWord);
   }
 
   // Loads and Stores.
   void ldr(Register rt, Address a, OperandSize sz = kDoubleWord) {
     if (a.type() == Address::PCOffset) {
       ASSERT(sz == kDoubleWord);
       EmitLoadRegLiteral(LDRpc, rt, a, sz);
@@ skipping 393 matching lines @@
     add(TMP, PP, Operand(kHeapObjectTag));
     str(TMP, Address(SP, -1 * kWordSize, Address::PreIndex));
   }
   void PopAndUntagPP() {
     ldr(PP, Address(SP, 1 * kWordSize, Address::PostIndex));
     sub(PP, PP, Operand(kHeapObjectTag));
   }
   void tst(Register rn, Operand o) {
     ands(ZR, rn, o);
   }
-  void tsti(Register rn, uint64_t imm) {
+  void tsti(Register rn, const Immediate& imm) {
     andis(ZR, rn, imm);
   }
 
   void LslImmediate(Register rd, Register rn, int shift) {
     add(rd, ZR, Operand(rn, LSL, shift));
   }
   void LsrImmediate(Register rd, Register rn, int shift) {
     add(rd, ZR, Operand(rn, LSR, shift));
   }
   void AsrImmediate(Register rd, Register rn, int shift) {
@@ skipping 501 matching lines @@
         op | (static_cast<int32_t>(crn) << kRnShift);
     Emit(encoding);
   }
 
   void EmitExceptionGenOp(ExceptionGenOp op, uint16_t imm) {
     const int32_t encoding =
         op | (static_cast<int32_t>(imm) << kImm16Shift);
     Emit(encoding);
   }
 
-  void EmitMoveWideOp(MoveWideOp op, Register rd, uint16_t imm, int hw_idx,
-                      OperandSize sz) {
+  void EmitMoveWideOp(MoveWideOp op, Register rd, const Immediate& imm,
+                      int hw_idx, OperandSize sz) {
     ASSERT((hw_idx >= 0) && (hw_idx <= 3));
     ASSERT((sz == kDoubleWord) || (sz == kWord) || (sz == kUnsignedWord));
     const int32_t size = (sz == kDoubleWord) ? B31 : 0;
     const int32_t encoding =
         op | size |
         (static_cast<int32_t>(rd) << kRdShift) |
         (static_cast<int32_t>(hw_idx) << kHWShift) |
-        (static_cast<int32_t>(imm) << kImm16Shift);
+        (static_cast<int32_t>(imm.value() & 0xffff) << kImm16Shift);
     Emit(encoding);
   }
 
   void EmitLoadStoreReg(LoadStoreRegOp op, Register rt, Address a,
                         OperandSize sz) {
     const Register crt = ConcreteRegister(rt);
     const int32_t size = Log2OperandSizeBytes(sz);
     const int32_t encoding =
         op | ((size & 0x3) << kSzShift) |
         (static_cast<int32_t>(crt) << kRtShift) |
         a.encoding();
     Emit(encoding);
   }
 
   void EmitLoadRegLiteral(LoadRegLiteralOp op, Register rt, Address a,
                           OperandSize sz) {
     ASSERT((sz == kDoubleWord) || (sz == kWord) || (sz == kUnsignedWord));
     ASSERT((rt != CSP) && (rt != R31));
     const Register crt = ConcreteRegister(rt);
     const int32_t size = (sz == kDoubleWord) ? B30 : 0;
     const int32_t encoding =
         op | size |
         (static_cast<int32_t>(crt) << kRtShift) |
         a.encoding();
     Emit(encoding);
   }
 
-  void EmitPCRelOp(PCRelOp op, Register rd, int64_t imm) {
-    ASSERT(Utils::IsInt(21, imm));
+  void EmitPCRelOp(PCRelOp op, Register rd, const Immediate& imm) {
+    ASSERT(Utils::IsInt(21, imm.value()));
     ASSERT((rd != R31) && (rd != CSP));
     const Register crd = ConcreteRegister(rd);
-    const int32_t loimm = (imm & 0x3) << 29;
-    const int32_t hiimm = ((imm >> 2) << kImm19Shift) & kImm19Mask;
+    const int32_t loimm = (imm.value() & 0x3) << 29;
+    const int32_t hiimm = ((imm.value() >> 2) << kImm19Shift) & kImm19Mask;
     const int32_t encoding =
         op | loimm | hiimm |
         (static_cast<int32_t>(crd) << kRdShift);
     Emit(encoding);
   }
 
   void EmitMiscDP2Source(MiscDP2SourceOp op,
                          Register rd, Register rn, Register rm,
                          OperandSize sz) {
     ASSERT((rd != CSP) && (rn != CSP) && (rm != CSP));
@@ skipping 128 matching lines @@
                                   Register value,
                                   Label* no_update);
 
   DISALLOW_ALLOCATION();
   DISALLOW_COPY_AND_ASSIGN(Assembler);
 };
 
 }  // namespace dart
 
 #endif  // VM_ASSEMBLER_ARM64_H_