Expands the use of Immediate and Operand wrappers.

runtime/vm/stub_code_mips.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/globals.h"
 #if defined(TARGET_ARCH_MIPS)
 
 #include "vm/assembler.h"
 #include "vm/code_generator.h"
 #include "vm/compiler.h"
@@ skipping 47 matching lines @@
   // Save current Context pointer into Isolate structure.
   __ sw(CTX, Address(A0, Isolate::top_context_offset()));
 
   // Cache Isolate pointer into CTX while executing runtime code.
   __ mov(CTX, A0);
 
 #if defined(DEBUG)
   { Label ok;
     // Check that we are always entering from Dart code.
     __ lw(T0, Address(A0, Isolate::vm_tag_offset()));
-    __ BranchEqual(T0, VMTag::kDartTagId, &ok);
+    __ BranchEqual(T0, Immediate(VMTag::kDartTagId), &ok);
     __ Stop("Not coming from Dart code.");
     __ Bind(&ok);
   }
 #endif
 
   // Mark that the isolate is executing VM code.
   __ sw(S5, Address(A0, Isolate::vm_tag_offset()));
 
   // Reserve space for arguments and align frame before entering C++ world.
   // NativeArguments are passed in registers.
@@ skipping 105 matching lines @@
   // Save current Context pointer into Isolate structure.
   __ sw(CTX, Address(A0, Isolate::top_context_offset()));
 
   // Cache Isolate pointer into CTX while executing native code.
   __ mov(CTX, A0);
 
 #if defined(DEBUG)
   { Label ok;
     // Check that we are always entering from Dart code.
     __ lw(T0, Address(A0, Isolate::vm_tag_offset()));
-    __ BranchEqual(T0, VMTag::kDartTagId, &ok);
+    __ BranchEqual(T0, Immediate(VMTag::kDartTagId), &ok);
     __ Stop("Not coming from Dart code.");
     __ Bind(&ok);
   }
 #endif
 
   // Mark that the isolate is executing Native code.
   __ sw(T5, Address(A0, Isolate::vm_tag_offset()));
 
   // Initialize NativeArguments structure and call native function.
   // Registers A0, A1, A2, and A3 are used.
@@ skipping 94 matching lines @@
   // Save current Context pointer into Isolate structure.
   __ sw(CTX, Address(A0, Isolate::top_context_offset()));
 
   // Cache Isolate pointer into CTX while executing native code.
   __ mov(CTX, A0);
 
 #if defined(DEBUG)
   { Label ok;
     // Check that we are always entering from Dart code.
     __ lw(T0, Address(A0, Isolate::vm_tag_offset()));
-    __ BranchEqual(T0, VMTag::kDartTagId, &ok);
+    __ BranchEqual(T0, Immediate(VMTag::kDartTagId), &ok);
     __ Stop("Not coming from Dart code.");
     __ Bind(&ok);
   }
 #endif
 
   // Mark that the isolate is executing Native code.
   __ sw(T5, Address(A0, Isolate::vm_tag_offset()));
 
   // Initialize NativeArguments structure and call native function.
   // Registers A0, A1, A2, and A3 are used.
@@ skipping 377 matching lines @@
   __ mov(T3, A1);  // Array length.
 
   // Check that length is a positive Smi.
   __ andi(CMPRES1, T3, Immediate(kSmiTagMask));
   __ bne(CMPRES1, ZR, &slow_case);
   __ bltz(T3, &slow_case);
 
   // Check for maximum allowed length.
   const intptr_t max_len =
       reinterpret_cast<int32_t>(Smi::New(Array::kMaxElements));
-  __ BranchUnsignedGreater(T3, max_len, &slow_case);
+  __ BranchUnsignedGreater(T3, Immediate(max_len), &slow_case);
 
   const intptr_t fixed_size = sizeof(RawArray) + kObjectAlignment - 1;
   __ LoadImmediate(T2, fixed_size);
   __ sll(T3, T3, 1);  // T3 is  a Smi.
   __ addu(T2, T2, T3);
   ASSERT(kSmiTagShift == 1);
   __ LoadImmediate(T3, ~(kObjectAlignment - 1));
   __ and_(T2, T2, T3);
 
   // T2: Allocation size.
@@ skipping 23 matching lines @@
   __ UpdateAllocationStatsWithSize(cid, T2, T4, space);
 
   // Initialize the tags.
   // T0: new object start as a tagged pointer.
   // T1: new object end address.
   // T2: allocation size.
   {
     Label overflow, done;
     const intptr_t shift = RawObject::kSizeTagPos - kObjectAlignmentLog2;
 
-    __ BranchUnsignedGreater(T2, RawObject::SizeTag::kMaxSizeTag, &overflow);
+    __ BranchUnsignedGreater(
+        T2, Immediate(RawObject::SizeTag::kMaxSizeTag), &overflow);
     __ b(&done);
     __ delay_slot()->sll(T2, T2, shift);
     __ Bind(&overflow);
     __ mov(T2, ZR);
     __ Bind(&done);
 
     // Get the class index and insert it into the tags.
     // T2: size and bit tags.
     __ LoadImmediate(TMP, RawObject::ClassIdTag::encode(cid));
     __ or_(T2, T2, TMP);
@@ skipping 677 matching lines @@
   // S5: IC data object (preserved).
   __ lw(T0, FieldAddress(S5, ICData::ic_data_offset()));
   // T0: ic_data_array with check entries: classes and target functions.
   __ AddImmediate(T0, Array::data_offset() - kHeapObjectTag);
   // T0: points directly to the first ic data array element.
 #if defined(DEBUG)
   // Check that first entry is for Smi/Smi.
   Label error, ok;
   const int32_t imm_smi_cid = reinterpret_cast<int32_t>(Smi::New(kSmiCid));
   __ lw(T4, Address(T0));
-  __ BranchNotEqual(T4, imm_smi_cid, &error);
+  __ BranchNotEqual(T4, Immediate(imm_smi_cid), &error);
   __ lw(T4, Address(T0, kWordSize));
-  __ BranchEqual(T4, imm_smi_cid, &ok);
+  __ BranchEqual(T4, Immediate(imm_smi_cid), &ok);
   __ Bind(&error);
   __ Stop("Incorrect IC data");
   __ Bind(&ok);
 #endif
   // Update counter.
   const intptr_t count_offset = ICData::CountIndexFor(num_args) * kWordSize;
   __ lw(T4, Address(T0, count_offset));
   __ AddImmediateDetectOverflow(T7, T4, Smi::RawValue(1), T5, T6);
   __ slt(CMPRES1, T5, ZR);  // T5 is < 0 if there was overflow.
   __ LoadImmediate(T4, Smi::RawValue(Smi::kMaxValue));
@@ skipping 21 matching lines @@
     Token::Kind kind) {
   __ TraceSimMsg("NArgsCheckInlineCacheStub");
   ASSERT(num_args > 0);
 #if defined(DEBUG)
   { Label ok;
     // Check that the IC data array has NumArgsTested() == num_args.
     // 'NumArgsTested' is stored in the least significant bits of 'state_bits'.
     __ lw(T0, FieldAddress(S5, ICData::state_bits_offset()));
     ASSERT(ICData::NumArgsTestedShift() == 0);  // No shift needed.
     __ andi(T0, T0, Immediate(ICData::NumArgsTestedMask()));
-    __ BranchEqual(T0, num_args, &ok);
+    __ BranchEqual(T0, Immediate(num_args), &ok);
     __ Stop("Incorrect stub for IC data");
     __ Bind(&ok);
   }
 #endif  // DEBUG
 
 
   // Check single stepping.
   Label stepping, done_stepping;
   __ LoadImmediate(T0, Isolate::CurrentAddress());
   __ lbu(T0, Address(T0, Isolate::single_step_offset()));
-  __ BranchNotEqual(T0, 0, &stepping);
+  __ BranchNotEqual(T0, Immediate(0), &stepping);
   __ Bind(&done_stepping);
 
   if (kind != Token::kILLEGAL) {
     Label not_smi_or_overflow;
     EmitFastSmiOp(assembler, kind, num_args, &not_smi_or_overflow);
     __ Bind(&not_smi_or_overflow);
   }
 
   // Load argument descriptor into S4.
   __ lw(S4, FieldAddress(S5, ICData::arguments_descriptor_offset()));
@@ skipping 54 matching lines @@
     __ addu(T3, T3, SP);
     __ lw(T3, Address(T3));
     __ LoadTaggedClassIdMayBeSmi(T3, T3);
   }
 
   const intptr_t entry_size = ICData::TestEntryLengthFor(num_args) * kWordSize;
   __ AddImmediate(T0, entry_size);  // Next entry.
   __ lw(T4, Address(T0));  // Next class ID.
 
   __ Bind(&test);
-  __ BranchNotEqual(T4, Smi::RawValue(kIllegalCid), &loop);  // Done?
+  __ BranchNotEqual(T4, Immediate(Smi::RawValue(kIllegalCid)), &loop);  // Done?
 
   // IC miss.
   // Restore return address.
   __ mov(RA, T2);
 
   // Compute address of arguments (first read number of arguments from
   // arguments descriptor array and then compute address on the stack).
   // T1: argument_count - 1 (smi).
   __ sll(T1, T1, 1);  // T1 is Smi.
   __ addu(T1, SP, T1);
@@ skipping 160 matching lines @@
     __ beq(T0, ZR, &ok);
     __ Stop("Incorrect IC data for unoptimized static call");
     __ Bind(&ok);
   }
 #endif  // DEBUG
 
   // Check single stepping.
   Label stepping, done_stepping;
   __ LoadImmediate(T0, Isolate::CurrentAddress());
   __ lbu(T0, Address(T0, Isolate::single_step_offset()));
-  __ BranchNotEqual(T0, 0, &stepping);
+  __ BranchNotEqual(T0, Immediate(0), &stepping);
   __ Bind(&done_stepping);
 
   // S5: IC data object (preserved).
   __ lw(T0, FieldAddress(S5, ICData::ic_data_offset()));
   // T0: ic_data_array with entries: target functions and count.
   __ AddImmediate(T0, Array::data_offset() - kHeapObjectTag);
   // T0: points directly to the first ic data array element.
   const intptr_t target_offset = ICData::TargetIndexFor(0) * kWordSize;
   const intptr_t count_offset = ICData::CountIndexFor(0) * kWordSize;
 
@@ skipping 126 matching lines @@
 }
 
 
 // Called only from unoptimized code. All relevant registers have been saved.
 // RA: return address.
 void StubCode::GenerateDebugStepCheckStub(Assembler* assembler) {
   // Check single stepping.
   Label stepping, done_stepping;
   __ lw(T0, FieldAddress(CTX, Context::isolate_offset()));
   __ lbu(T0, Address(T0, Isolate::single_step_offset()));
-  __ BranchNotEqual(T0, 0, &stepping);
+  __ BranchNotEqual(T0, Immediate(0), &stepping);
   __ Bind(&done_stepping);
 
   __ Ret();
 
   // Call single step callback in debugger.
   __ Bind(&stepping);
   __ EnterStubFrame();
   __ addiu(SP, SP, Immediate(-1 * kWordSize));
   __ sw(RA, Address(SP, 0 * kWordSize));  // Return address.
   __ CallRuntime(kSingleStepHandlerRuntimeEntry, 0);
@@ skipping 14 matching lines @@
   __ TraceSimMsg("SubtypeNTestCacheStub");
   ASSERT((1 <= n) && (n <= 3));
   if (n > 1) {
     // Get instance type arguments.
     __ LoadClass(T0, A0);
     // Compute instance type arguments into T1.
     Label has_no_type_arguments;
     __ LoadImmediate(T1, reinterpret_cast<intptr_t>(Object::null()));
     __ lw(T2, FieldAddress(T0,
         Class::type_arguments_field_offset_in_words_offset()));
-    __ BranchEqual(T2, Class::kNoTypeArguments, &has_no_type_arguments);
+    __ BranchEqual(
+        T2, Immediate(Class::kNoTypeArguments), &has_no_type_arguments);
     __ sll(T2, T2, 2);
     __ addu(T2, A0, T2);  // T2 <- A0 + T2 * 4
     __ lw(T1, FieldAddress(T2, 0));
     __ Bind(&has_no_type_arguments);
   }
   __ LoadClassId(T0, A0);
   // A0: instance.
   // A1: instantiator type arguments or NULL.
   // A2: SubtypeTestCache.
   // T0: instance class id.
@@ skipping 232 matching lines @@
 // RA: return address.
 // SP + 4: left operand.
 // SP + 0: right operand.
 // Returns: CMPRES1 is zero if equal, non-zero otherwise.
 void StubCode::GenerateUnoptimizedIdenticalWithNumberCheckStub(
     Assembler* assembler) {
   // Check single stepping.
   Label stepping, done_stepping;
   __ lw(T0, FieldAddress(CTX, Context::isolate_offset()));
   __ lbu(T0, Address(T0, Isolate::single_step_offset()));
-  __ BranchNotEqual(T0, 0, &stepping);
+  __ BranchNotEqual(T0, Immediate(0), &stepping);
   __ Bind(&done_stepping);
 
   const Register temp1 = T2;
   const Register temp2 = T3;
   const Register left = T1;
   const Register right = T0;
   __ lw(left, Address(SP, 1 * kWordSize));
   __ lw(right, Address(SP, 0 * kWordSize));
   GenerateIdenticalWithNumberCheckStub(assembler, left, right, temp1, temp2);
   __ Ret();
@@ skipping 23 matching lines @@
   const Register right = T0;
   __ lw(left, Address(SP, 1 * kWordSize));
   __ lw(right, Address(SP, 0 * kWordSize));
   GenerateIdenticalWithNumberCheckStub(assembler, left, right, temp1, temp2);
   __ Ret();
 }
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_MIPS