| OLD | NEW |
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| (Empty) | |
| 1 .syntax unified |
| 2 .cpu cortex-a8 |
| 3 .eabi_attribute 27, 3 |
| 4 .eabi_attribute 28, 1 |
| 5 .fpu neon |
| 6 .eabi_attribute 20, 1 |
| 7 .eabi_attribute 21, 1 |
| 8 .eabi_attribute 23, 3 |
| 9 .eabi_attribute 24, 1 |
| 10 .eabi_attribute 25, 1 |
| 11 .eabi_attribute 26, 2 |
| 12 .eabi_attribute 30, 2 |
| 13 .eabi_attribute 34, 1 |
| 14 .eabi_attribute 18, 4 |
| 15 .thumb |
| 16 .file "chacha_vec.c" |
| 17 .text |
| 18 .align 2 |
| 19 .global CRYPTO_chacha_20_neon |
| 20 .thumb |
| 21 .thumb_func |
| 22 .type CRYPTO_chacha_20_neon, %function |
| 23 CRYPTO_chacha_20_neon: |
| 24 @ args = 8, pretend = 0, frame = 296 |
| 25 @ frame_needed = 1, uses_anonymous_args = 0 |
| 26 @ link register save eliminated. |
| 27 push {r4, r5, r6, r7, r8, r9, sl, fp} |
| 28 fstmfdd sp!, {d8, d9, d10, d11, d12, d13, d14, d15} |
| 29 sub sp, sp, #296 |
| 30 add r7, sp, #0 |
| 31 movw ip, #43691 |
| 32 movt ip, 43690 |
| 33 str r2, [r7, #192] |
| 34 sub sp, sp, #96 |
| 35 ldr r4, [r7, #192] |
| 36 ldr r6, [r7, #392] |
| 37 ldr r2, .L38+16 |
| 38 umull r4, ip, ip, r4 |
| 39 ldr r6, [r6, #0] |
| 40 ldr r8, [r7, #392] |
| 41 add r4, sp, #15 |
| 42 str r3, [r7, #236] |
| 43 bic r4, r4, #15 |
| 44 str r6, [r7, #172] |
| 45 str r4, [r7, #196] |
| 46 str r0, [r7, #184] |
| 47 lsrs ip, ip, #7 |
| 48 str r1, [r7, #180] |
| 49 ldmia r2, {r0, r1, r2, r3} |
| 50 ldr r4, [r8, #4] |
| 51 ldr r5, [r7, #236] |
| 52 vld1.64 {d24-d25}, [r5:64] |
| 53 vldr d26, [r5, #16] |
| 54 vldr d27, [r5, #24] |
| 55 ldr fp, [r7, #196] |
| 56 ldr r8, [r7, #396] |
| 57 ldr r5, [r7, #172] |
| 58 add r6, fp, #64 |
| 59 str r4, [r7, #292] |
| 60 mov r4, #0 |
| 61 str r8, [r7, #280] |
| 62 str r5, [r7, #288] |
| 63 str r4, [r7, #284] |
| 64 stmia r6, {r0, r1, r2, r3} |
| 65 vldr d22, [fp, #64] |
| 66 vldr d23, [fp, #72] |
| 67 vldr d20, [r7, #280] |
| 68 vldr d21, [r7, #288] |
| 69 str ip, [r7, #188] |
| 70 beq .L20 |
| 71 lsl r6, ip, #1 |
| 72 ldr r1, [fp, #68] |
| 73 add r3, r6, ip |
| 74 str r6, [r7, #176] |
| 75 ldr r2, [fp, #72] |
| 76 add r8, r8, #2 |
| 77 ldr r5, [fp, #76] |
| 78 vldr d18, .L38 |
| 79 vldr d19, .L38+8 |
| 80 str r4, [r7, #232] |
| 81 ldr r6, [r7, #180] |
| 82 ldr r4, [r7, #184] |
| 83 str r0, [r7, #220] |
| 84 str r1, [r7, #216] |
| 85 str r8, [r7, #200] |
| 86 str r2, [r7, #212] |
| 87 str r3, [r7, #204] |
| 88 str r5, [r7, #208] |
| 89 str r6, [r7, #244] |
| 90 str r4, [r7, #240] |
| 91 .L4: |
| 92 ldr r6, [r7, #236] |
| 93 vadd.i32 q8, q10, q9 |
| 94 ldr r5, [r7, #236] |
| 95 vmov q15, q13 @ v4si |
| 96 ldr r8, [r7, #232] |
| 97 vmov q3, q12 @ v4si |
| 98 ldr r6, [r6, #4] |
| 99 vmov q2, q11 @ v4si |
| 100 ldr fp, [r7, #200] |
| 101 vmov q5, q10 @ v4si |
| 102 ldr r4, [r7, #236] |
| 103 vmov q1, q13 @ v4si |
| 104 add ip, r8, fp |
| 105 ldr r5, [r5, #0] |
| 106 ldr r0, [r7, #236] |
| 107 add r8, r7, #208 |
| 108 ldr r1, [r7, #236] |
| 109 vmov q0, q12 @ v4si |
| 110 str r6, [r7, #260] |
| 111 vmov q4, q11 @ v4si |
| 112 ldr r6, [r7, #392] |
| 113 ldmia r8, {r8, r9, sl, fp} |
| 114 ldr r0, [r0, #8] |
| 115 ldr r1, [r1, #12] |
| 116 str r5, [r7, #224] |
| 117 ldr r5, [r4, #24] |
| 118 ldr r3, [r4, #28] |
| 119 ldr r2, [r6, #4] |
| 120 str r0, [r7, #256] |
| 121 str r1, [r7, #228] |
| 122 str r5, [r7, #272] |
| 123 ldr r5, [r6, #0] |
| 124 movs r6, #0 |
| 125 ldr r0, [r4, #16] |
| 126 ldr r1, [r4, #20] |
| 127 movs r4, #10 |
| 128 str r2, [r7, #20] |
| 129 str r3, [r7, #276] |
| 130 str r9, [r7, #268] |
| 131 mov r9, r6 |
| 132 str r4, [r7, #248] |
| 133 ldr r2, [r7, #256] |
| 134 ldr r3, [r7, #228] |
| 135 str r8, [r7, #252] |
| 136 mov r8, sl |
| 137 ldr r6, [r7, #272] |
| 138 mov sl, ip |
| 139 str r1, [r7, #264] |
| 140 ldr ip, [r7, #20] |
| 141 str r6, [r7, #256] |
| 142 mov r6, r5 |
| 143 ldr r1, [r7, #260] |
| 144 mov r5, r0 |
| 145 ldr r0, [r7, #224] |
| 146 b .L39 |
| 147 .L40: |
| 148 .align 3 |
| 149 .L38: |
| 150 .word 1 |
| 151 .word 0 |
| 152 .word 0 |
| 153 .word 0 |
| 154 .word .LANCHOR0 |
| 155 .L39: |
| 156 .L3: |
| 157 vadd.i32 q4, q4, q0 |
| 158 add r8, r8, r1 |
| 159 vadd.i32 q2, q2, q3 |
| 160 str r8, [r7, #260] |
| 161 veor q5, q5, q4 |
| 162 ldr r8, [r7, #268] |
| 163 veor q8, q8, q2 |
| 164 add fp, fp, r0 |
| 165 str fp, [r7, #272] |
| 166 add r8, r8, r2 |
| 167 vrev32.16 q5, q5 |
| 168 str r8, [r7, #268] |
| 169 vrev32.16 q8, q8 |
| 170 vadd.i32 q1, q1, q5 |
| 171 vadd.i32 q15, q15, q8 |
| 172 ldr r8, [r7, #272] |
| 173 veor q0, q1, q0 |
| 174 ldr r4, [r7, #252] |
| 175 veor q3, q15, q3 |
| 176 eor sl, sl, r8 |
| 177 ldr r8, [r7, #268] |
| 178 add fp, r4, r3 |
| 179 vshl.i32 q7, q0, #12 |
| 180 ldr r4, [r7, #260] |
| 181 vshl.i32 q6, q3, #12 |
| 182 eor r6, r6, r8 |
| 183 eor r9, r9, r4 |
| 184 ldr r4, [r7, #264] |
| 185 vsri.32 q7, q0, #20 |
| 186 ror r8, r6, #16 |
| 187 ldr r6, [r7, #256] |
| 188 eor ip, ip, fp |
| 189 vsri.32 q6, q3, #20 |
| 190 ror sl, sl, #16 |
| 191 ror r9, r9, #16 |
| 192 add r5, r5, sl |
| 193 vadd.i32 q4, q4, q7 |
| 194 str r5, [r7, #228] |
| 195 vadd.i32 q2, q2, q6 |
| 196 add r5, r4, r9 |
| 197 add r4, r6, r8 |
| 198 ldr r6, [r7, #276] |
| 199 ror ip, ip, #16 |
| 200 veor q5, q4, q5 |
| 201 veor q8, q2, q8 |
| 202 add r6, r6, ip |
| 203 str r6, [r7, #256] |
| 204 eors r1, r1, r5 |
| 205 ldr r6, [r7, #228] |
| 206 vshl.i32 q3, q5, #8 |
| 207 vshl.i32 q14, q8, #8 |
| 208 eors r2, r2, r4 |
| 209 eors r0, r0, r6 |
| 210 ldr r6, [r7, #256] |
| 211 vsri.32 q3, q5, #24 |
| 212 ror r1, r1, #20 |
| 213 eors r3, r3, r6 |
| 214 ldr r6, [r7, #272] |
| 215 ror r0, r0, #20 |
| 216 vsri.32 q14, q8, #24 |
| 217 adds r6, r0, r6 |
| 218 str r6, [r7, #276] |
| 219 ldr r6, [r7, #260] |
| 220 vadd.i32 q1, q1, q3 |
| 221 vadd.i32 q15, q15, q14 |
| 222 ror r2, r2, #20 |
| 223 adds r6, r1, r6 |
| 224 str r6, [r7, #252] |
| 225 ldr r6, [r7, #268] |
| 226 veor q6, q15, q6 |
| 227 veor q7, q1, q7 |
| 228 ror r3, r3, #20 |
| 229 adds r6, r2, r6 |
| 230 str r6, [r7, #272] |
| 231 ldr r6, [r7, #276] |
| 232 vshl.i32 q0, q6, #7 |
| 233 vshl.i32 q5, q7, #7 |
| 234 add fp, r3, fp |
| 235 eor sl, r6, sl |
| 236 ldr r6, [r7, #252] |
| 237 eor ip, fp, ip |
| 238 vsri.32 q0, q6, #25 |
| 239 eor r9, r6, r9 |
| 240 ldr r6, [r7, #272] |
| 241 ror sl, sl, #24 |
| 242 vsri.32 q5, q7, #25 |
| 243 eor r8, r6, r8 |
| 244 ldr r6, [r7, #228] |
| 245 ror r9, r9, #24 |
| 246 ror ip, ip, #24 |
| 247 add r6, sl, r6 |
| 248 str r6, [r7, #268] |
| 249 ldr r6, [r7, #256] |
| 250 add r5, r9, r5 |
| 251 str r5, [r7, #264] |
| 252 vext.32 q5, q5, q5, #1 |
| 253 add r5, ip, r6 |
| 254 ldr r6, [r7, #268] |
| 255 vext.32 q0, q0, q0, #1 |
| 256 vadd.i32 q4, q4, q5 |
| 257 eors r0, r0, r6 |
| 258 ldr r6, [r7, #264] |
| 259 vadd.i32 q2, q2, q0 |
| 260 vext.32 q3, q3, q3, #3 |
| 261 ror r8, r8, #24 |
| 262 eors r1, r1, r6 |
| 263 vext.32 q14, q14, q14, #3 |
| 264 add r4, r8, r4 |
| 265 ldr r6, [r7, #276] |
| 266 veor q3, q4, q3 |
| 267 veor q14, q2, q14 |
| 268 eors r2, r2, r4 |
| 269 ror r1, r1, #25 |
| 270 vext.32 q1, q1, q1, #2 |
| 271 adds r6, r1, r6 |
| 272 str r6, [r7, #276] |
| 273 vext.32 q15, q15, q15, #2 |
| 274 ldr r6, [r7, #252] |
| 275 eors r3, r3, r5 |
| 276 ror r2, r2, #25 |
| 277 vrev32.16 q8, q14 |
| 278 adds r6, r2, r6 |
| 279 vrev32.16 q3, q3 |
| 280 str r6, [r7, #260] |
| 281 vadd.i32 q1, q1, q3 |
| 282 ldr r6, [r7, #272] |
| 283 vadd.i32 q15, q15, q8 |
| 284 ror r3, r3, #25 |
| 285 veor q5, q1, q5 |
| 286 adds r6, r3, r6 |
| 287 veor q0, q15, q0 |
| 288 str r6, [r7, #256] |
| 289 ldr r6, [r7, #260] |
| 290 ror r0, r0, #25 |
| 291 add fp, r0, fp |
| 292 vshl.i32 q6, q5, #12 |
| 293 eor sl, r6, sl |
| 294 ldr r6, [r7, #276] |
| 295 vshl.i32 q14, q0, #12 |
| 296 eor r8, fp, r8 |
| 297 eor ip, r6, ip |
| 298 ldr r6, [r7, #256] |
| 299 vsri.32 q6, q5, #20 |
| 300 ror sl, sl, #16 |
| 301 eor r9, r6, r9 |
| 302 ror r6, r8, #16 |
| 303 vsri.32 q14, q0, #20 |
| 304 ldr r8, [r7, #264] |
| 305 ror ip, ip, #16 |
| 306 add r5, sl, r5 |
| 307 add r8, r6, r8 |
| 308 add r4, ip, r4 |
| 309 str r4, [r7, #228] |
| 310 eor r0, r8, r0 |
| 311 str r5, [r7, #272] |
| 312 vadd.i32 q4, q4, q6 |
| 313 ldr r5, [r7, #228] |
| 314 vadd.i32 q2, q2, q14 |
| 315 ldr r4, [r7, #268] |
| 316 ror r0, r0, #20 |
| 317 veor q3, q4, q3 |
| 318 eors r1, r1, r5 |
| 319 veor q0, q2, q8 |
| 320 str r8, [r7, #264] |
| 321 str r0, [r7, #20] |
| 322 add fp, r0, fp |
| 323 ldr r8, [r7, #272] |
| 324 ror r9, r9, #16 |
| 325 ldr r0, [r7, #276] |
| 326 add r4, r9, r4 |
| 327 str fp, [r7, #252] |
| 328 ror r1, r1, #20 |
| 329 add fp, r1, r0 |
| 330 eor r2, r8, r2 |
| 331 ldr r0, [r7, #252] |
| 332 eors r3, r3, r4 |
| 333 vshl.i32 q5, q3, #8 |
| 334 str r4, [r7, #224] |
| 335 vshl.i32 q8, q0, #8 |
| 336 ldr r4, [r7, #260] |
| 337 ldr r5, [r7, #256] |
| 338 ror r2, r2, #20 |
| 339 ror r3, r3, #20 |
| 340 eors r6, r6, r0 |
| 341 adds r5, r3, r5 |
| 342 add r8, r2, r4 |
| 343 vsri.32 q5, q3, #24 |
| 344 ldr r4, [r7, #264] |
| 345 eor r9, r5, r9 |
| 346 eor ip, fp, ip |
| 347 vsri.32 q8, q0, #24 |
| 348 eor sl, r8, sl |
| 349 ror r6, r6, #24 |
| 350 ldr r0, [r7, #272] |
| 351 str r5, [r7, #268] |
| 352 adds r4, r6, r4 |
| 353 ldr r5, [r7, #228] |
| 354 vadd.i32 q1, q1, q5 |
| 355 str r4, [r7, #264] |
| 356 vadd.i32 q15, q15, q8 |
| 357 ldr r4, [r7, #224] |
| 358 ror ip, ip, #24 |
| 359 ror sl, sl, #24 |
| 360 ror r9, r9, #24 |
| 361 add r5, ip, r5 |
| 362 add r0, sl, r0 |
| 363 str r5, [r7, #256] |
| 364 add r5, r9, r4 |
| 365 str r0, [r7, #276] |
| 366 veor q6, q1, q6 |
| 367 ldr r4, [r7, #20] |
| 368 veor q14, q15, q14 |
| 369 ldr r0, [r7, #264] |
| 370 eors r3, r3, r5 |
| 371 vshl.i32 q0, q6, #7 |
| 372 vext.32 q1, q1, q1, #2 |
| 373 eors r0, r0, r4 |
| 374 ldr r4, [r7, #276] |
| 375 str r0, [r7, #272] |
| 376 vshl.i32 q3, q14, #7 |
| 377 eors r2, r2, r4 |
| 378 ldr r4, [r7, #272] |
| 379 ldr r0, [r7, #256] |
| 380 vsri.32 q0, q6, #25 |
| 381 ror r2, r2, #25 |
| 382 ror r3, r3, #25 |
| 383 eors r1, r1, r0 |
| 384 vsri.32 q3, q14, #25 |
| 385 ror r0, r4, #25 |
| 386 ldr r4, [r7, #248] |
| 387 ror r1, r1, #25 |
| 388 vext.32 q5, q5, q5, #1 |
| 389 subs r4, r4, #1 |
| 390 str r4, [r7, #248] |
| 391 vext.32 q15, q15, q15, #2 |
| 392 vext.32 q8, q8, q8, #1 |
| 393 vext.32 q0, q0, q0, #3 |
| 394 vext.32 q3, q3, q3, #3 |
| 395 bne .L3 |
| 396 ldr r4, [r7, #256] |
| 397 vadd.i32 q4, q11, q4 |
| 398 str r2, [r7, #256] |
| 399 vadd.i32 q14, q10, q9 |
| 400 ldr r2, [r7, #244] |
| 401 vld1.64 {d12-d13}, [r2:64] |
| 402 str r4, [r7, #272] |
| 403 veor q4, q4, q6 |
| 404 ldr r4, [r7, #220] |
| 405 vadd.i32 q10, q10, q5 |
| 406 ldr r2, [r7, #216] |
| 407 vadd.i32 q0, q12, q0 |
| 408 add fp, fp, r4 |
| 409 str ip, [r7, #20] |
| 410 ldr r4, [r7, #212] |
| 411 mov ip, sl |
| 412 str r0, [r7, #224] |
| 413 mov sl, r8 |
| 414 mov r0, r5 |
| 415 ldr r8, [r7, #252] |
| 416 mov r5, r6 |
| 417 add sl, sl, r2 |
| 418 mov r6, r9 |
| 419 ldr r2, [r7, #208] |
| 420 ldr r9, [r7, #268] |
| 421 vadd.i32 q1, q13, q1 |
| 422 vadd.i32 q2, q11, q2 |
| 423 str r1, [r7, #260] |
| 424 add r9, r9, r4 |
| 425 add r4, r8, r2 |
| 426 ldr r8, [r7, #232] |
| 427 vadd.i32 q3, q12, q3 |
| 428 vadd.i32 q15, q13, q15 |
| 429 str r3, [r7, #228] |
| 430 add r2, r8, #2 |
| 431 vadd.i32 q8, q14, q8 |
| 432 add ip, r2, ip |
| 433 ldr r2, [r7, #240] |
| 434 vst1.64 {d8-d9}, [r2:64] |
| 435 ldr r2, [r7, #244] |
| 436 ldr r3, [r7, #276] |
| 437 vldr d8, [r2, #16] |
| 438 vldr d9, [r2, #24] |
| 439 ldr r1, [r7, #264] |
| 440 veor q0, q0, q4 |
| 441 add r8, r8, #3 |
| 442 str r8, [r7, #232] |
| 443 ldr r8, [r7, #240] |
| 444 vstr d0, [r8, #16] |
| 445 vstr d1, [r8, #24] |
| 446 vldr d0, [r2, #32] |
| 447 vldr d1, [r2, #40] |
| 448 veor q1, q1, q0 |
| 449 vstr d2, [r8, #32] |
| 450 vstr d3, [r8, #40] |
| 451 vldr d2, [r2, #48] |
| 452 vldr d3, [r2, #56] |
| 453 veor q10, q10, q1 |
| 454 vstr d20, [r8, #48] |
| 455 vstr d21, [r8, #56] |
| 456 vldr d8, [r2, #64] |
| 457 vldr d9, [r2, #72] |
| 458 veor q2, q2, q4 |
| 459 vstr d4, [r8, #64] |
| 460 vstr d5, [r8, #72] |
| 461 vldr d10, [r2, #80] |
| 462 vldr d11, [r2, #88] |
| 463 veor q3, q3, q5 |
| 464 vstr d6, [r8, #80] |
| 465 vstr d7, [r8, #88] |
| 466 vldr d12, [r2, #96] |
| 467 vldr d13, [r2, #104] |
| 468 veor q15, q15, q6 |
| 469 vstr d30, [r8, #96] |
| 470 vstr d31, [r8, #104] |
| 471 vldr d20, [r2, #112] |
| 472 vldr d21, [r2, #120] |
| 473 veor q8, q8, q10 |
| 474 vstr d16, [r8, #112] |
| 475 vstr d17, [r8, #120] |
| 476 mov r8, r2 |
| 477 ldr r2, [r2, #128] |
| 478 vadd.i32 q10, q14, q9 |
| 479 eor r2, fp, r2 |
| 480 ldr fp, [r7, #240] |
| 481 vadd.i32 q10, q10, q9 |
| 482 str r2, [fp, #128] |
| 483 ldr r2, [r8, #132] |
| 484 eor r2, sl, r2 |
| 485 str r2, [fp, #132] |
| 486 ldr r2, [r8, #136] |
| 487 eor r2, r9, r2 |
| 488 str r2, [fp, #136] |
| 489 ldr r2, [r8, #140] |
| 490 eors r2, r2, r4 |
| 491 str r2, [fp, #140] |
| 492 ldr r2, [r7, #236] |
| 493 ldr r4, [r8, #144] |
| 494 ldr r2, [r2, #0] |
| 495 str r4, [r7, #168] |
| 496 ldr r4, [r7, #224] |
| 497 add r8, r4, r2 |
| 498 ldr r2, [r7, #168] |
| 499 ldr r4, [r7, #236] |
| 500 eor r8, r8, r2 |
| 501 ldr r2, [r7, #244] |
| 502 str r8, [fp, #144] |
| 503 ldr r4, [r4, #4] |
| 504 ldr r2, [r2, #148] |
| 505 str r2, [r7, #36] |
| 506 ldr r2, [r7, #260] |
| 507 add r8, r2, r4 |
| 508 ldr r4, [r7, #36] |
| 509 ldr r2, [r7, #236] |
| 510 eor r8, r8, r4 |
| 511 ldr r4, [r7, #244] |
| 512 str r8, [fp, #148] |
| 513 ldr r2, [r2, #8] |
| 514 ldr r4, [r4, #152] |
| 515 str r4, [r7, #32] |
| 516 ldr r4, [r7, #256] |
| 517 add r8, r4, r2 |
| 518 ldr r2, [r7, #32] |
| 519 eor r8, r8, r2 |
| 520 str r8, [fp, #152] |
| 521 ldr r2, [r7, #244] |
| 522 ldr r4, [r7, #236] |
| 523 ldr r2, [r2, #156] |
| 524 ldr r4, [r4, #12] |
| 525 str r2, [r7, #28] |
| 526 ldr r2, [r7, #228] |
| 527 add r8, r2, r4 |
| 528 ldr r4, [r7, #28] |
| 529 ldr r2, [r7, #244] |
| 530 eor r8, r8, r4 |
| 531 str r8, [fp, #156] |
| 532 ldr r8, [r7, #236] |
| 533 ldr r2, [r2, #160] |
| 534 ldr r4, [r8, #16] |
| 535 adds r0, r0, r4 |
| 536 ldr r4, [r7, #244] |
| 537 eors r0, r0, r2 |
| 538 str r0, [fp, #160] |
| 539 ldr r0, [r8, #20] |
| 540 ldr r2, [r4, #164] |
| 541 adds r1, r1, r0 |
| 542 ldr r0, [r7, #272] |
| 543 eors r1, r1, r2 |
| 544 str r1, [fp, #164] |
| 545 ldr r2, [r8, #24] |
| 546 ldr r1, [r4, #168] |
| 547 adds r2, r0, r2 |
| 548 eors r2, r2, r1 |
| 549 str r2, [fp, #168] |
| 550 ldr r1, [r8, #28] |
| 551 ldr r2, [r4, #172] |
| 552 adds r3, r3, r1 |
| 553 eors r3, r3, r2 |
| 554 str r3, [fp, #172] |
| 555 ldr r3, [r4, #176] |
| 556 eor r3, ip, r3 |
| 557 str r3, [fp, #176] |
| 558 ldr r3, [r4, #180] |
| 559 ldr r4, [r7, #392] |
| 560 eors r6, r6, r3 |
| 561 str r6, [fp, #180] |
| 562 ldr r6, [r7, #244] |
| 563 ldr r2, [r4, #0] |
| 564 ldr r3, [r6, #184] |
| 565 adds r5, r5, r2 |
| 566 eors r5, r5, r3 |
| 567 str r5, [fp, #184] |
| 568 ldr r2, [r6, #188] |
| 569 adds r6, r6, #192 |
| 570 ldr r3, [r4, #4] |
| 571 str r6, [r7, #244] |
| 572 ldr r0, [r7, #20] |
| 573 ldr r1, [r7, #232] |
| 574 adds r4, r0, r3 |
| 575 eors r4, r4, r2 |
| 576 ldr r2, [r7, #204] |
| 577 str r4, [fp, #188] |
| 578 add fp, fp, #192 |
| 579 cmp r1, r2 |
| 580 str fp, [r7, #240] |
| 581 bne .L4 |
| 582 ldr r4, [r7, #188] |
| 583 ldr r3, [r7, #176] |
| 584 ldr r6, [r7, #184] |
| 585 adds r5, r3, r4 |
| 586 ldr r8, [r7, #180] |
| 587 lsls r5, r5, #6 |
| 588 adds r4, r6, r5 |
| 589 add r5, r8, r5 |
| 590 .L2: |
| 591 ldr fp, [r7, #192] |
| 592 movw r3, #43691 |
| 593 movt r3, 43690 |
| 594 ldr r6, [r7, #192] |
| 595 umull fp, r3, r3, fp |
| 596 lsrs r3, r3, #7 |
| 597 add r3, r3, r3, lsl #1 |
| 598 sub r3, r6, r3, lsl #6 |
| 599 lsrs r6, r3, #6 |
| 600 beq .L5 |
| 601 add r1, r5, #16 |
| 602 add r2, r4, #16 |
| 603 mov r0, r6 |
| 604 vldr d30, .L41 |
| 605 vldr d31, .L41+8 |
| 606 .L6: |
| 607 vmov q8, q10 @ v4si |
| 608 movs r3, #10 |
| 609 vmov q1, q13 @ v4si |
| 610 vmov q14, q12 @ v4si |
| 611 vmov q3, q11 @ v4si |
| 612 .L7: |
| 613 vadd.i32 q3, q3, q14 |
| 614 subs r3, r3, #1 |
| 615 veor q2, q8, q3 |
| 616 vrev32.16 q2, q2 |
| 617 vadd.i32 q8, q1, q2 |
| 618 veor q9, q8, q14 |
| 619 vshl.i32 q14, q9, #12 |
| 620 vsri.32 q14, q9, #20 |
| 621 vadd.i32 q3, q3, q14 |
| 622 veor q2, q3, q2 |
| 623 vshl.i32 q9, q2, #8 |
| 624 vsri.32 q9, q2, #24 |
| 625 vadd.i32 q8, q8, q9 |
| 626 vext.32 q9, q9, q9, #3 |
| 627 veor q14, q8, q14 |
| 628 vext.32 q1, q8, q8, #2 |
| 629 vshl.i32 q8, q14, #7 |
| 630 vsri.32 q8, q14, #25 |
| 631 vext.32 q8, q8, q8, #1 |
| 632 vadd.i32 q3, q3, q8 |
| 633 veor q2, q3, q9 |
| 634 vrev32.16 q2, q2 |
| 635 vadd.i32 q9, q1, q2 |
| 636 veor q8, q9, q8 |
| 637 vshl.i32 q14, q8, #12 |
| 638 vsri.32 q14, q8, #20 |
| 639 vadd.i32 q3, q3, q14 |
| 640 veor q2, q3, q2 |
| 641 vshl.i32 q8, q2, #8 |
| 642 vsri.32 q8, q2, #24 |
| 643 vadd.i32 q9, q9, q8 |
| 644 vext.32 q8, q8, q8, #1 |
| 645 veor q14, q9, q14 |
| 646 vext.32 q1, q9, q9, #2 |
| 647 vshl.i32 q9, q14, #7 |
| 648 vsri.32 q9, q14, #25 |
| 649 vext.32 q14, q9, q9, #3 |
| 650 bne .L7 |
| 651 vadd.i32 q8, q10, q8 |
| 652 subs r0, r0, #1 |
| 653 vadd.i32 q3, q11, q3 |
| 654 vldr d0, [r1, #-16] |
| 655 vldr d1, [r1, #-8] |
| 656 vadd.i32 q14, q12, q14 |
| 657 vadd.i32 q1, q13, q1 |
| 658 veor q3, q3, q0 |
| 659 vstr d6, [r2, #-16] |
| 660 vstr d7, [r2, #-8] |
| 661 vadd.i32 q10, q10, q15 |
| 662 vld1.64 {d8-d9}, [r1:64] |
| 663 veor q14, q14, q4 |
| 664 vst1.64 {d28-d29}, [r2:64] |
| 665 vldr d10, [r1, #16] |
| 666 vldr d11, [r1, #24] |
| 667 veor q1, q1, q5 |
| 668 vstr d2, [r2, #16] |
| 669 vstr d3, [r2, #24] |
| 670 vldr d18, [r1, #32] |
| 671 vldr d19, [r1, #40] |
| 672 add r1, r1, #64 |
| 673 veor q8, q8, q9 |
| 674 vstr d16, [r2, #32] |
| 675 vstr d17, [r2, #40] |
| 676 add r2, r2, #64 |
| 677 bne .L6 |
| 678 lsls r6, r6, #6 |
| 679 adds r4, r4, r6 |
| 680 adds r5, r5, r6 |
| 681 .L5: |
| 682 ldr r6, [r7, #192] |
| 683 ands ip, r6, #63 |
| 684 beq .L1 |
| 685 vmov q8, q10 @ v4si |
| 686 movs r3, #10 |
| 687 vmov q14, q13 @ v4si |
| 688 vmov q9, q12 @ v4si |
| 689 vmov q15, q11 @ v4si |
| 690 .L10: |
| 691 vadd.i32 q15, q15, q9 |
| 692 subs r3, r3, #1 |
| 693 veor q8, q8, q15 |
| 694 vrev32.16 q8, q8 |
| 695 vadd.i32 q3, q14, q8 |
| 696 veor q9, q3, q9 |
| 697 vshl.i32 q14, q9, #12 |
| 698 vsri.32 q14, q9, #20 |
| 699 vadd.i32 q15, q15, q14 |
| 700 veor q9, q15, q8 |
| 701 vshl.i32 q8, q9, #8 |
| 702 vsri.32 q8, q9, #24 |
| 703 vadd.i32 q9, q3, q8 |
| 704 vext.32 q8, q8, q8, #3 |
| 705 veor q2, q9, q14 |
| 706 vext.32 q14, q9, q9, #2 |
| 707 vshl.i32 q9, q2, #7 |
| 708 vsri.32 q9, q2, #25 |
| 709 vext.32 q9, q9, q9, #1 |
| 710 vadd.i32 q15, q15, q9 |
| 711 veor q3, q15, q8 |
| 712 vrev32.16 q3, q3 |
| 713 vadd.i32 q14, q14, q3 |
| 714 veor q8, q14, q9 |
| 715 vshl.i32 q9, q8, #12 |
| 716 vsri.32 q9, q8, #20 |
| 717 vadd.i32 q15, q15, q9 |
| 718 veor q3, q15, q3 |
| 719 vshl.i32 q8, q3, #8 |
| 720 vsri.32 q8, q3, #24 |
| 721 vadd.i32 q14, q14, q8 |
| 722 vext.32 q8, q8, q8, #1 |
| 723 veor q3, q14, q9 |
| 724 vext.32 q14, q14, q14, #2 |
| 725 vshl.i32 q9, q3, #7 |
| 726 vsri.32 q9, q3, #25 |
| 727 vext.32 q9, q9, q9, #3 |
| 728 bne .L10 |
| 729 cmp ip, #15 |
| 730 vadd.i32 q11, q11, q15 |
| 731 bhi .L37 |
| 732 ldr fp, [r7, #196] |
| 733 vst1.64 {d22-d23}, [fp:128] |
| 734 .L14: |
| 735 ldr r6, [r7, #192] |
| 736 and r3, r6, #48 |
| 737 cmp ip, r3 |
| 738 bls .L1 |
| 739 adds r0, r5, r3 |
| 740 adds r1, r4, r3 |
| 741 add r2, r0, #16 |
| 742 add r6, r1, #16 |
| 743 cmp r1, r2 |
| 744 it cc |
| 745 cmpcc r0, r6 |
| 746 rsb r9, r3, ip |
| 747 ite cc |
| 748 movcc r2, #0 |
| 749 movcs r2, #1 |
| 750 cmp r9, #15 |
| 751 ite ls |
| 752 movls r2, #0 |
| 753 andhi r2, r2, #1 |
| 754 lsr r8, r9, #4 |
| 755 eor r2, r2, #1 |
| 756 cmp r8, #0 |
| 757 it eq |
| 758 orreq r2, r2, #1 |
| 759 lsl sl, r8, #4 |
| 760 cbnz r2, .L35 |
| 761 ldr fp, [r7, #196] |
| 762 add r6, fp, r3 |
| 763 .L17: |
| 764 vld1.8 {q8}, [r0]! |
| 765 adds r2, r2, #1 |
| 766 cmp r8, r2 |
| 767 vld1.8 {q9}, [r6]! |
| 768 veor q8, q9, q8 |
| 769 vst1.8 {q8}, [r1]! |
| 770 bhi .L17 |
| 771 cmp r9, sl |
| 772 add r3, r3, sl |
| 773 beq .L1 |
| 774 .L35: |
| 775 ldr r0, [r7, #196] |
| 776 .L25: |
| 777 ldrb r2, [r5, r3] @ zero_extendqisi2 |
| 778 ldrb r1, [r3, r0] @ zero_extendqisi2 |
| 779 eors r2, r2, r1 |
| 780 strb r2, [r4, r3] |
| 781 adds r3, r3, #1 |
| 782 cmp ip, r3 |
| 783 bhi .L25 |
| 784 .L1: |
| 785 add r7, r7, #296 |
| 786 mov sp, r7 |
| 787 fldmfdd sp!, {d8, d9, d10, d11, d12, d13, d14, d15} |
| 788 pop {r4, r5, r6, r7, r8, r9, sl, fp} |
| 789 bx lr |
| 790 .L37: |
| 791 cmp ip, #31 |
| 792 vld1.64 {d0-d1}, [r5:64] |
| 793 vadd.i32 q9, q12, q9 |
| 794 veor q11, q11, q0 |
| 795 vst1.64 {d22-d23}, [r4:64] |
| 796 bls .L12 |
| 797 cmp ip, #47 |
| 798 vldr d2, [r5, #16] |
| 799 vldr d3, [r5, #24] |
| 800 vadd.i32 q13, q13, q14 |
| 801 veor q9, q9, q1 |
| 802 vstr d18, [r4, #16] |
| 803 vstr d19, [r4, #24] |
| 804 bls .L13 |
| 805 vadd.i32 q8, q8, q10 |
| 806 vldr d0, [r5, #32] |
| 807 vldr d1, [r5, #40] |
| 808 ldr r6, [r7, #196] |
| 809 vstr d16, [r6, #48] |
| 810 vstr d17, [r6, #56] |
| 811 veor q8, q13, q0 |
| 812 vstr d16, [r4, #32] |
| 813 vstr d17, [r4, #40] |
| 814 b .L14 |
| 815 .L12: |
| 816 ldr r8, [r7, #196] |
| 817 vstr d18, [r8, #16] |
| 818 vstr d19, [r8, #24] |
| 819 b .L14 |
| 820 .L20: |
| 821 ldr r5, [r7, #180] |
| 822 ldr r4, [r7, #184] |
| 823 b .L2 |
| 824 .L13: |
| 825 ldr r6, [r7, #196] |
| 826 vstr d26, [r6, #32] |
| 827 vstr d27, [r6, #40] |
| 828 b .L14 |
| 829 .L42: |
| 830 .align 3 |
| 831 .L41: |
| 832 .word 1 |
| 833 .word 0 |
| 834 .word 0 |
| 835 .word 0 |
| 836 .size CRYPTO_chacha_20_neon, .-CRYPTO_chacha_20_neon |
| 837 .section .rodata |
| 838 .align 3 |
| 839 .LANCHOR0 = . + 0 |
| 840 .LC0: |
| 841 .word 1634760805 |
| 842 .word 857760878 |
| 843 .word 2036477234 |
| 844 .word 1797285236 |
| 845 .ident "GCC: (crosstool-NG linaro-1.13.1-4.7-2012.10-20121022 - Linaro
GCC 2012.10) 4.7.3 20121001 (prerelease)" |
| 846 .section .note.GNU-stack,"",%progbits |
| OLD | NEW |
|---|
Chromium Code Reviews
Issue 59083010:
third_party/openssl: add ChaCha20+Poly1305 support.
Base URL: https://chromium.googlesource.com/chromium/deps/openssl.git@master