Subzero: Make tests stricter after fixing "lock foo" bundling bug.

tests_lit/llvm2ice_tests/nacl-atomic-intrinsics.ll

 ; This tests each of the supported NaCl atomic instructions for every
 ; size allowed.
 
 ; RUN: %llvm2ice -O2 --verbose none %s \
 ; RUN:   | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \
 ; RUN:   | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
 ; RUN: %llvm2ice -O2 --verbose none %s \
 ; RUN:   | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \
 ; RUN:   | llvm-objdump -d --symbolize -x86-asm-syntax=intel - \
 ; RUN:   | FileCheck --check-prefix=CHECKO2 %s
 ; RUN: %llvm2ice -Om1 --verbose none %s \
 ; RUN:   | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \
 ; RUN:   | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
 ; RUN: %llvm2ice --verbose none %s | FileCheck --check-prefix=ERRORS %s
 ; RUN: %llvm2iceinsts %s | %szdiff %s | FileCheck --check-prefix=DUMP %s
 ; RUN: %llvm2iceinsts --pnacl %s | %szdiff %s \
 ; RUN:                           | FileCheck --check-prefix=DUMP %s
 
-; TODO(jvoung): Uh... normally pnacl-llc is not supposed to separate the
-; lock from its instruction w/ bundle padding, but when processing .s
-; files with llvm-mc it seems be ocassionally wrong!
-; https://code.google.com/p/nativeclient/issues/detail?id=3929
-; That makes the current "lock" checks avoid using CHECK-NEXT.
-
 declare i8 @llvm.nacl.atomic.load.i8(i8*, i32)
 declare i16 @llvm.nacl.atomic.load.i16(i16*, i32)
 declare i32 @llvm.nacl.atomic.load.i32(i32*, i32)
 declare i64 @llvm.nacl.atomic.load.i64(i64*, i32)
 declare void @llvm.nacl.atomic.store.i8(i8, i8*, i32)
 declare void @llvm.nacl.atomic.store.i16(i16, i16*, i32)
 declare void @llvm.nacl.atomic.store.i32(i32, i32*, i32)
 declare void @llvm.nacl.atomic.store.i64(i64, i64*, i32)
 declare i8 @llvm.nacl.atomic.rmw.i8(i32, i8*, i8, i32)
 declare i16 @llvm.nacl.atomic.rmw.i16(i32, i16*, i16, i32)
@@ skipping 182 matching lines @@
 define i32 @test_atomic_rmw_add_16(i32 %iptr, i32 %v) {
 entry:
   %trunc = trunc i32 %v to i16
   %ptr = inttoptr i32 %iptr to i16*
   %a = call i16 @llvm.nacl.atomic.rmw.i16(i32 1, i16* %ptr, i16 %trunc, i32 6)
   %a_ext = zext i16 %a to i32
   ret i32 %a_ext
 }
 ; CHECK-LABEL: test_atomic_rmw_add_16
 ; CHECK: lock
-; Should be using NEXT: see issue 3929
-; CHECK: xadd word {{.*}}, [[REG:.*]]
+; CHECK-NEXT: xadd word {{.*}}, [[REG:.*]]
 ; CHECK: mov {{.*}}, [[REG]]
 
 define i32 @test_atomic_rmw_add_32(i32 %iptr, i32 %v) {
 entry:
   %ptr = inttoptr i32 %iptr to i32*
   %a = call i32 @llvm.nacl.atomic.rmw.i32(i32 1, i32* %ptr, i32 %v, i32 6)
   ret i32 %a
 }
 ; CHECK-LABEL: test_atomic_rmw_add_32
 ; CHECK: lock
@@ skipping 108 matching lines @@
 entry:
   %trunc = trunc i32 %v to i8
   %ptr = inttoptr i32 %iptr to i8*
   %a = call i8 @llvm.nacl.atomic.rmw.i8(i32 2, i8* %ptr, i8 %trunc, i32 6)
   %a_ext = zext i8 %a to i32
   ret i32 %a_ext
 }
 ; CHECK-LABEL: test_atomic_rmw_sub_8
 ; CHECK: neg [[REG:.*]]
 ; CHECK: lock
-; Should be using NEXT: see issue 3929
-; CHECK: xadd byte {{.*}}, [[REG]]
+; CHECK-NEXT: xadd byte {{.*}}, [[REG]]
 ; CHECK: mov {{.*}}, [[REG]]
 
 define i32 @test_atomic_rmw_sub_16(i32 %iptr, i32 %v) {
 entry:
   %trunc = trunc i32 %v to i16
   %ptr = inttoptr i32 %iptr to i16*
   %a = call i16 @llvm.nacl.atomic.rmw.i16(i32 2, i16* %ptr, i16 %trunc, i32 6)
   %a_ext = zext i16 %a to i32
   ret i32 %a_ext
 }
@@ skipping 23 matching lines @@
 }
 ; CHECK-LABEL: test_atomic_rmw_sub_64
 ; CHECK: push ebx
 ; CHECK: mov eax, dword ptr [{{.*}}]
 ; CHECK: mov edx, dword ptr [{{.*}} + 4]
 ; CHECK: mov ebx, eax
 ; CHECK: sub ebx, {{.*e.[^x]}}
 ; CHECK: mov ecx, edx
 ; CHECK: sbb ecx, {{.*e.[^x]}}
 ; CHECK: lock
-; Should be using NEXT: see issue 3929
-; CHECK: cmpxchg8b qword ptr [e{{.[^x]}}]
+; CHECK-NEXT: cmpxchg8b qword ptr [e{{.[^x]}}]
 ; CHECK: jne -{{[0-9]}}
 
 
 define i32 @test_atomic_rmw_sub_32_ignored(i32 %iptr, i32 %v) {
 entry:
   %ptr = inttoptr i32 %iptr to i32*
   %ignored = call i32 @llvm.nacl.atomic.rmw.i32(i32 2, i32* %ptr, i32 %v, i32 6)
   ret i32 %v
 }
 ; Could use "lock sub" instead of "neg; lock xadd"
@@ skipping 150 matching lines @@
 entry:
   %ptr = inttoptr i32 %iptr to i32*
   %ignored = call i32 @llvm.nacl.atomic.rmw.i32(i32 4, i32* %ptr, i32 %v, i32 6)
   ret i32 %v
 }
 ; CHECK-LABEL: test_atomic_rmw_and_32_ignored
 ; Could just "lock and"
 ; CHECK: mov eax, dword ptr
 ; CHECK: and
 ; CHECK: lock
-; Should be using NEXT: see issue 3929
-; CHECK: cmpxchg dword ptr [e{{[^a].}}]
+; CHECK-NEXT: cmpxchg dword ptr [e{{[^a].}}]
 ; CHECK: jne -{{[0-9]}}
 
 ;; xor
 
 define i32 @test_atomic_rmw_xor_8(i32 %iptr, i32 %v) {
 entry:
   %trunc = trunc i32 %v to i8
   %ptr = inttoptr i32 %iptr to i8*
   %a = call i8 @llvm.nacl.atomic.rmw.i8(i32 5, i8* %ptr, i8 %trunc, i32 6)
   %a_ext = zext i8 %a to i32
@@ skipping 179 matching lines @@
                                                i64 %desired, i32 6, i32 6)
   ret i64 %old
 }
 ; CHECK-LABEL: test_atomic_cmpxchg_64
 ; CHECK: push ebx
 ; CHECK-DAG: mov edx
 ; CHECK-DAG: mov eax
 ; CHECK-DAG: mov ecx
 ; CHECK-DAG: mov ebx
 ; CHECK: lock
-; Should be using NEXT: see issue 3929
-; CHECK: cmpxchg8b qword ptr [e{{.[^x]}}]
+; CHECK-NEXT: cmpxchg8b qword ptr [e{{.[^x]}}]
 ; edx and eax are already the return registers, so they don't actually
 ; need to be reshuffled via movs. The next test stores the result
 ; somewhere, so in that case they do need to be mov'ed.
 
 ; Test a case where %old really does need to be copied out of edx:eax.
 define void @test_atomic_cmpxchg_64_store(i32 %ret_iptr, i32 %iptr, i64 %expected, i64 %desired) {
 entry:
   %ptr = inttoptr i32 %iptr to i64*
   %old = call i64 @llvm.nacl.atomic.cmpxchg.i64(i64* %ptr, i64 %expected,
                                                 i64 %desired, i32 6, i32 6)
@@ skipping 33 matching lines @@
 ; CHECK-DAG: mov edx
 ; CHECK-DAG: mov eax
 ; CHECK-DAG: mov ecx
 ; CHECK-DAG: mov ebx
 ; Ptr cannot be eax, ebx, ecx, or edx (used up for the expected and desired).
 ; It also cannot be ebp since we use that for alloca. Also make sure it's
 ; not esp, since that's the stack pointer and mucking with it will break
 ; the later use_ptr function call.
 ; That pretty much leaves esi, or edi as the only viable registers.
 ; CHECK: lock
-; Should be using NEXT: see issue 3929
-; CHECK: cmpxchg8b qword ptr [e{{[ds]}}i]
+; CHECK-NEXT: cmpxchg8b qword ptr [e{{[ds]}}i]
 ; CHECK: call use_ptr
 
 define i32 @test_atomic_cmpxchg_32_ignored(i32 %iptr, i32 %expected, i32 %desired) {
 entry:
   %ptr = inttoptr i32 %iptr to i32*
   %ignored = call i32 @llvm.nacl.atomic.cmpxchg.i32(i32* %ptr, i32 %expected,
                                                     i32 %desired, i32 6, i32 6)
   ret i32 0
 }
 ; CHECK-LABEL: test_atomic_cmpxchg_32_ignored
 ; CHECK: mov eax, {{.*}}
 ; CHECK: lock
 ; CHECK-NEXT: cmpxchg dword ptr [e{{[^a].}}]
 
 define i64 @test_atomic_cmpxchg_64_ignored(i32 %iptr, i64 %expected, i64 %desired) {
 entry:
   %ptr = inttoptr i32 %iptr to i64*
   %ignored = call i64 @llvm.nacl.atomic.cmpxchg.i64(i64* %ptr, i64 %expected,
                                                     i64 %desired, i32 6, i32 6)
   ret i64 0
 }
 ; CHECK-LABEL: test_atomic_cmpxchg_64_ignored
 ; CHECK: push ebx
 ; CHECK-DAG: mov edx
 ; CHECK-DAG: mov eax
 ; CHECK-DAG: mov ecx
 ; CHECK-DAG: mov ebx
 ; CHECK: lock
-; Should be using NEXT: see issue 3929
-; CHECK: cmpxchg8b qword ptr [e{{.[^x]}}]
+; CHECK-NEXT: cmpxchg8b qword ptr [e{{.[^x]}}]
 
 ;;;; Fence and is-lock-free.
 
 define void @test_atomic_fence() {
 entry:
   call void @llvm.nacl.atomic.fence(i32 6)
   ret void
 }
 ; CHECK-LABEL: test_atomic_fence
 ; CHECK: mfence
@@ skipping 58 matching lines @@
   ret i32 %z
 }
 ; CHECK-LABEL: test_atomic_is_lock_free_can_dce
 ; CHECK: mov {{.*}}, 1
 ; CHECK: ret
 ; CHECK: add
 ; CHECK: ret
 
 ; ERRORS-NOT: ICE translation error
 ; DUMP-NOT: SZ