Lift register and condition code enums out into their own file.

src/IceTargetLoweringX8632.cpp

 //===- subzero/src/IceTargetLoweringX8632.cpp - x86-32 lowering -----------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file implements the TargetLoweringX8632 class, which
 // consists almost entirely of the lowering sequence for each
 // high-level instruction.  It also implements
 // TargetX8632Fast::postLower() which does the simplest possible
 // register allocation for the "fast" target.
 //
 //===----------------------------------------------------------------------===//
 
 #include "IceDefs.h"
 #include "IceCfg.h"
 #include "IceCfgNode.h"
 #include "IceClFlags.h"
 #include "IceInstX8632.h"
 #include "IceOperand.h"
+#include "IceRegistersX8632.h"
 #include "IceTargetLoweringX8632.def"
 #include "IceTargetLoweringX8632.h"
 #include "llvm/ADT/DenseMap.h"
 #include "llvm/Support/MathExtras.h"
 #include "llvm/Support/CommandLine.h"
 
 namespace Ice {
 
 namespace {
 
@@ skipping 10 matching lines @@
 // table by hand, good execution tests are helpful.
 //
 // The last two columns describe the case when the operands are vectors
 // of floating point values.  For most fcmp conditions, there is a clear
 // mapping to a single x86 cmpps instruction variant.  Some fcmp
 // conditions require special code to handle and these are marked in the
 // table with a Cmpps_Invalid predicate.
 const struct TableFcmp_ {
   uint32_t Default;
   bool SwapScalarOperands;
-  InstX8632::BrCond C1, C2;
+  CondX86::BrCond C1, C2;
   bool SwapVectorOperands;
-  InstX8632Cmpps::CmppsCond Predicate;
+  CondX86::CmppsCond Predicate;
 } TableFcmp[] = {
 #define X(val, dflt, swapS, C1, C2, swapV, pred)                               \
-  {                                                                            \
-    dflt, swapS, InstX8632Br::C1, InstX8632Br::C2, swapV, InstX8632Cmpps::pred \
-  }                                                                            \
+  { dflt, swapS, CondX86::C1, CondX86::C2, swapV, CondX86::pred }              \
   ,
       FCMPX8632_TABLE
 #undef X
 };
 const size_t TableFcmpSize = llvm::array_lengthof(TableFcmp);
 
 // The following table summarizes the logic for lowering the icmp instruction
 // for i32 and narrower types.  Each icmp condition has a clear mapping to an
 // x86 conditional branch instruction.
 
 const struct TableIcmp32_ {
-  InstX8632::BrCond Mapping;
+  CondX86::BrCond Mapping;
 } TableIcmp32[] = {
 #define X(val, C_32, C1_64, C2_64, C3_64)                                      \
-  { InstX8632Br::C_32 }                                                        \
+  { CondX86::C_32 }                                                            \
   ,
     ICMPX8632_TABLE
 #undef X
   };
 const size_t TableIcmp32Size = llvm::array_lengthof(TableIcmp32);
 
 // The following table summarizes the logic for lowering the icmp instruction
 // for the i64 type.  For Eq and Ne, two separate 32-bit comparisons and
 // conditional branches are needed.  For the other conditions, three separate
 // conditional branches are needed.
 const struct TableIcmp64_ {
-  InstX8632::BrCond C1, C2, C3;
+  CondX86::BrCond C1, C2, C3;
 } TableIcmp64[] = {
 #define X(val, C_32, C1_64, C2_64, C3_64)                                      \
-  { InstX8632Br::C1_64, InstX8632Br::C2_64, InstX8632Br::C3_64 }               \
+  { CondX86::C1_64, CondX86::C2_64, CondX86::C3_64 }                           \
   ,
     ICMPX8632_TABLE
 #undef X
   };
 const size_t TableIcmp64Size = llvm::array_lengthof(TableIcmp64);
 
-InstX8632::BrCond getIcmp32Mapping(InstIcmp::ICond Cond) {
+CondX86::BrCond getIcmp32Mapping(InstIcmp::ICond Cond) {
   size_t Index = static_cast<size_t>(Cond);
   assert(Index < TableIcmp32Size);
   return TableIcmp32[Index].Mapping;
 }
 
 const struct TableTypeX8632Attributes_ {
   Type InVectorElementType;
 } TableTypeX8632Attributes[] = {
 #define X(tag, elementty, cvt, sdss, pack, width)                              \
   { elementty }                                                                \
@@ skipping 148 matching lines @@
 #undef X
   }
 }
 
 } // end of anonymous namespace
 
 TargetX8632::TargetX8632(Cfg *Func)
     : TargetLowering(Func), InstructionSet(CLInstructionSet),
       IsEbpBasedFrame(false), NeedsStackAlignment(false), FrameSizeLocals(0),
       SpillAreaSizeBytes(0), NextLabelNumber(0), ComputedLiveRanges(false),
-      PhysicalRegisters(VarList(Reg_NUM)) {
+      PhysicalRegisters(VarList(RegX8632::Reg_NUM)) {
   // TODO: Don't initialize IntegerRegisters and friends every time.
   // Instead, initialize in some sort of static initializer for the
   // class.
-  llvm::SmallBitVector IntegerRegisters(Reg_NUM);
-  llvm::SmallBitVector IntegerRegistersI8(Reg_NUM);
-  llvm::SmallBitVector FloatRegisters(Reg_NUM);
-  llvm::SmallBitVector VectorRegisters(Reg_NUM);
-  llvm::SmallBitVector InvalidRegisters(Reg_NUM);
-  ScratchRegs.resize(Reg_NUM);
-#define X(val, init, name, name16, name8, scratch, preserved, stackptr,        \
+  llvm::SmallBitVector IntegerRegisters(RegX8632::Reg_NUM);
+  llvm::SmallBitVector IntegerRegistersI8(RegX8632::Reg_NUM);
+  llvm::SmallBitVector FloatRegisters(RegX8632::Reg_NUM);
+  llvm::SmallBitVector VectorRegisters(RegX8632::Reg_NUM);
+  llvm::SmallBitVector InvalidRegisters(RegX8632::Reg_NUM);
+  ScratchRegs.resize(RegX8632::Reg_NUM);
+#define X(val, encode, name, name16, name8, scratch, preserved, stackptr,      \
           frameptr, isI8, isInt, isFP)                                         \
-  IntegerRegisters[val] = isInt;                                               \
-  IntegerRegistersI8[val] = isI8;                                              \
-  FloatRegisters[val] = isFP;                                                  \
-  VectorRegisters[val] = isFP;                                                 \
-  ScratchRegs[val] = scratch;
+  IntegerRegisters[RegX8632::val] = isInt;                                     \
+  IntegerRegistersI8[RegX8632::val] = isI8;                                    \
+  FloatRegisters[RegX8632::val] = isFP;                                        \
+  VectorRegisters[RegX8632::val] = isFP;                                       \
+  ScratchRegs[RegX8632::val] = scratch;
   REGX8632_TABLE;
 #undef X
   TypeToRegisterSet[IceType_void] = InvalidRegisters;
   TypeToRegisterSet[IceType_i1] = IntegerRegistersI8;
   TypeToRegisterSet[IceType_i8] = IntegerRegistersI8;
   TypeToRegisterSet[IceType_i16] = IntegerRegisters;
   TypeToRegisterSet[IceType_i32] = IntegerRegisters;
   TypeToRegisterSet[IceType_i64] = IntegerRegisters;
   TypeToRegisterSet[IceType_f32] = FloatRegisters;
   TypeToRegisterSet[IceType_f64] = FloatRegisters;
@@ skipping 159 matching lines @@
 }
 
 bool TargetX8632::doBranchOpt(Inst *I, const CfgNode *NextNode) {
   if (InstX8632Br *Br = llvm::dyn_cast<InstX8632Br>(I)) {
     return Br->optimizeBranch(NextNode);
   }
   return false;
 }
 
 IceString TargetX8632::RegNames[] = {
-#define X(val, init, name, name16, name8, scratch, preserved, stackptr,        \
+#define X(val, encode, name, name16, name8, scratch, preserved, stackptr,      \
           frameptr, isI8, isInt, isFP)                                         \
   name,
   REGX8632_TABLE
 #undef X
 };
 
 Variable *TargetX8632::getPhysicalRegister(SizeT RegNum) {
   assert(RegNum < PhysicalRegisters.size());
   Variable *Reg = PhysicalRegisters[RegNum];
   if (Reg == NULL) {
     CfgNode *Node = NULL; // NULL means multi-block lifetime
     Reg = Func->makeVariable(IceType_i32, Node);
     Reg->setRegNum(RegNum);
     PhysicalRegisters[RegNum] = Reg;
   }
   return Reg;
 }
 
 IceString TargetX8632::getRegName(SizeT RegNum, Type Ty) const {
-  assert(RegNum < Reg_NUM);
+  assert(RegNum < RegX8632::Reg_NUM);
   static IceString RegNames8[] = {
-#define X(val, init, name, name16, name8, scratch, preserved, stackptr,        \
+#define X(val, encode, name, name16, name8, scratch, preserved, stackptr,      \
           frameptr, isI8, isInt, isFP)                                         \
   name8,
     REGX8632_TABLE
 #undef X
   };
   static IceString RegNames16[] = {
-#define X(val, init, name, name16, name8, scratch, preserved, stackptr,        \
+#define X(val, encode, name, name16, name8, scratch, preserved, stackptr,      \
           frameptr, isI8, isInt, isFP)                                         \
   name16,
     REGX8632_TABLE
 #undef X
   };
   switch (Ty) {
   case IceType_i1:
   case IceType_i8:
     return RegNames8[RegNum];
   case IceType_i16:
@@ skipping 36 matching lines @@
 
   for (SizeT I = 0, E = Args.size(); I < E && NumXmmArgs < X86_MAX_XMM_ARGS;
        ++I) {
     Variable *Arg = Args[I];
     Type Ty = Arg->getType();
     if (!isVectorType(Ty))
       continue;
     // Replace Arg in the argument list with the home register.  Then
     // generate an instruction in the prolog to copy the home register
     // to the assigned location of Arg.
-    int32_t RegNum = Reg_xmm0 + NumXmmArgs;
+    int32_t RegNum = RegX8632::Reg_xmm0 + NumXmmArgs;
     ++NumXmmArgs;
     IceString Name = "home_reg:" + Arg->getName();
     const CfgNode *DefNode = NULL;
     Variable *RegisterArg = Func->makeVariable(Ty, DefNode, Name);
     RegisterArg->setRegNum(RegNum);
     RegisterArg->setIsArg(Func);
     Arg->setIsArg(Func, false);
 
     Args[I] = RegisterArg;
     Context.insert(InstAssign::create(Func, Arg, RegisterArg));
@@ skipping 215 matching lines @@
       _push(getPhysicalRegister(i), SuppressStackAdjustment);
     }
   }
   Ctx->statsUpdateRegistersSaved(NumCallee);
 
   // Generate "push ebp; mov ebp, esp"
   if (IsEbpBasedFrame) {
     assert((RegsUsed & getRegisterSet(RegSet_FramePointer, RegSet_None))
                .count() == 0);
     PreservedRegsSizeBytes += 4;
-    Variable *ebp = getPhysicalRegister(Reg_ebp);
-    Variable *esp = getPhysicalRegister(Reg_esp);
+    Variable *ebp = getPhysicalRegister(RegX8632::Reg_ebp);
+    Variable *esp = getPhysicalRegister(RegX8632::Reg_esp);
     const bool SuppressStackAdjustment = true;
     _push(ebp, SuppressStackAdjustment);
     _mov(ebp, esp);
   }
 
   // Align the variables area. SpillAreaPaddingBytes is the size of
   // the region after the preserved registers and before the spill
   // areas.
   uint32_t SpillAreaPaddingBytes = 0;
   if (SpillAreaAlignmentBytes) {
@@ skipping 17 matching lines @@
 
   // Align esp if necessary.
   if (NeedsStackAlignment) {
     uint32_t StackOffset = X86_RET_IP_SIZE_BYTES + PreservedRegsSizeBytes;
     uint32_t StackSize = applyStackAlignment(StackOffset + SpillAreaSizeBytes);
     SpillAreaSizeBytes = StackSize - StackOffset;
   }
 
   // Generate "sub esp, SpillAreaSizeBytes"
   if (SpillAreaSizeBytes)
-    _sub(getPhysicalRegister(Reg_esp),
+    _sub(getPhysicalRegister(RegX8632::Reg_esp),
          Ctx->getConstantInt32(IceType_i32, SpillAreaSizeBytes));
   Ctx->statsUpdateFrameBytes(SpillAreaSizeBytes);
 
   resetStackAdjustment();
 
   // Fill in stack offsets for stack args, and copy args into registers
   // for those that were register-allocated.  Args are pushed right to
   // left, so Arg[0] is closest to the stack/frame pointer.
   Variable *FramePtr = getPhysicalRegister(getFrameOrStackReg());
   size_t BasicFrameOffset = PreservedRegsSizeBytes + X86_RET_IP_SIZE_BYTES;
@@ skipping 89 matching lines @@
   if (RI == E)
     return;
 
   // Convert the reverse_iterator position into its corresponding
   // (forward) iterator position.
   InstList::iterator InsertPoint = RI.base();
   --InsertPoint;
   Context.init(Node);
   Context.setInsertPoint(InsertPoint);
 
-  Variable *esp = getPhysicalRegister(Reg_esp);
+  Variable *esp = getPhysicalRegister(RegX8632::Reg_esp);
   if (IsEbpBasedFrame) {
-    Variable *ebp = getPhysicalRegister(Reg_ebp);
+    Variable *ebp = getPhysicalRegister(RegX8632::Reg_ebp);
     _mov(esp, ebp);
     _pop(ebp);
   } else {
     // add esp, SpillAreaSizeBytes
     if (SpillAreaSizeBytes)
       _add(esp, Ctx->getConstantInt32(IceType_i32, SpillAreaSizeBytes));
   }
 
   // Add pop instructions for preserved registers.
   llvm::SmallBitVector CalleeSaves =
       getRegisterSet(RegSet_CalleeSave, RegSet_None);
   for (SizeT i = 0; i < CalleeSaves.size(); ++i) {
     SizeT j = CalleeSaves.size() - i - 1;
-    if (j == Reg_ebp && IsEbpBasedFrame)
+    if (j == RegX8632::Reg_ebp && IsEbpBasedFrame)
       continue;
     if (CalleeSaves[j] && RegsUsed[j]) {
       _pop(getPhysicalRegister(j));
     }
   }
 }
 
 template <typename T> struct PoolTypeConverter {};
 
 template <> struct PoolTypeConverter<float> {
@@ skipping 136 matching lines @@
     return OperandX8632Mem::create(Func, IceType_i32, Mem->getBase(), Offset,
                                    Mem->getIndex(), Mem->getShift(),
                                    Mem->getSegmentRegister());
   }
   llvm_unreachable("Unsupported operand type");
   return NULL;
 }
 
 llvm::SmallBitVector TargetX8632::getRegisterSet(RegSetMask Include,
                                                  RegSetMask Exclude) const {
-  llvm::SmallBitVector Registers(Reg_NUM);
+  llvm::SmallBitVector Registers(RegX8632::Reg_NUM);
 
-#define X(val, init, name, name16, name8, scratch, preserved, stackptr,        \
+#define X(val, encode, name, name16, name8, scratch, preserved, stackptr,      \
           frameptr, isI8, isInt, isFP)                                         \
   if (scratch && (Include & RegSet_CallerSave))                                \
-    Registers[val] = true;                                                     \
+    Registers[RegX8632::val] = true;                                           \
   if (preserved && (Include & RegSet_CalleeSave))                              \
-    Registers[val] = true;                                                     \
+    Registers[RegX8632::val] = true;                                           \
   if (stackptr && (Include & RegSet_StackPointer))                             \
-    Registers[val] = true;                                                     \
+    Registers[RegX8632::val] = true;                                           \
   if (frameptr && (Include & RegSet_FramePointer))                             \
-    Registers[val] = true;                                                     \
+    Registers[RegX8632::val] = true;                                           \
   if (scratch && (Exclude & RegSet_CallerSave))                                \
-    Registers[val] = false;                                                    \
+    Registers[RegX8632::val] = false;                                          \
   if (preserved && (Exclude & RegSet_CalleeSave))                              \
-    Registers[val] = false;                                                    \
+    Registers[RegX8632::val] = false;                                          \
   if (stackptr && (Exclude & RegSet_StackPointer))                             \
-    Registers[val] = false;                                                    \
+    Registers[RegX8632::val] = false;                                          \
   if (frameptr && (Exclude & RegSet_FramePointer))                             \
-    Registers[val] = false;
+    Registers[RegX8632::val] = false;
 
   REGX8632_TABLE
 
 #undef X
 
   return Registers;
 }
 
 void TargetX8632::lowerAlloca(const InstAlloca *Inst) {
   IsEbpBasedFrame = true;
   // Conservatively require the stack to be aligned.  Some stack
   // adjustment operations implemented below assume that the stack is
   // aligned before the alloca.  All the alloca code ensures that the
   // stack alignment is preserved after the alloca.  The stack alignment
   // restriction can be relaxed in some cases.
   NeedsStackAlignment = true;
 
   // TODO(sehr,stichnot): minimize the number of adjustments of esp, etc.
-  Variable *esp = getPhysicalRegister(Reg_esp);
+  Variable *esp = getPhysicalRegister(RegX8632::Reg_esp);
   Operand *TotalSize = legalize(Inst->getSizeInBytes());
   Variable *Dest = Inst->getDest();
   uint32_t AlignmentParam = Inst->getAlignInBytes();
   // For default align=0, set it to the real value 1, to avoid any
   // bit-manipulation problems below.
   AlignmentParam = std::max(AlignmentParam, 1u);
 
   // LLVM enforces power of 2 alignment.
   assert((AlignmentParam & (AlignmentParam - 1)) == 0);
   assert((X86_STACK_ALIGNMENT_BYTES & (X86_STACK_ALIGNMENT_BYTES - 1)) == 0);
@@ skipping 70 matching lines @@
     case InstArithmetic::Sub:
       _mov(T_Lo, Src0Lo);
       _sub(T_Lo, Src1Lo);
       _mov(DestLo, T_Lo);
       _mov(T_Hi, Src0Hi);
       _sbb(T_Hi, Src1Hi);
       _mov(DestHi, T_Hi);
       break;
     case InstArithmetic::Mul: {
       Variable *T_1 = NULL, *T_2 = NULL, *T_3 = NULL;
-      Variable *T_4Lo = makeReg(IceType_i32, Reg_eax);
-      Variable *T_4Hi = makeReg(IceType_i32, Reg_edx);
+      Variable *T_4Lo = makeReg(IceType_i32, RegX8632::Reg_eax);
+      Variable *T_4Hi = makeReg(IceType_i32, RegX8632::Reg_edx);
       // gcc does the following:
       // a=b*c ==>
       //   t1 = b.hi; t1 *=(imul) c.lo
       //   t2 = c.hi; t2 *=(imul) b.lo
       //   t3:eax = b.lo
       //   t4.hi:edx,t4.lo:eax = t3:eax *(mul) c.lo
       //   a.lo = t4.lo
       //   t4.hi += t1
       //   t4.hi += t2
       //   a.hi = t4.hi
       // The mul instruction cannot take an immediate operand.
       Src1Lo = legalize(Src1Lo, Legal_Reg | Legal_Mem);
       _mov(T_1, Src0Hi);
       _imul(T_1, Src1Lo);
       _mov(T_2, Src1Hi);
       _imul(T_2, Src0Lo);
-      _mov(T_3, Src0Lo, Reg_eax);
+      _mov(T_3, Src0Lo, RegX8632::Reg_eax);
       _mul(T_4Lo, T_3, Src1Lo);
       // The mul instruction produces two dest variables, edx:eax.  We
       // create a fake definition of edx to account for this.
       Context.insert(InstFakeDef::create(Func, T_4Hi, T_4Lo));
       _mov(DestLo, T_4Lo);
       _add(T_4Hi, T_1);
       _add(T_4Hi, T_2);
       _mov(DestHi, T_4Hi);
     } break;
     case InstArithmetic::Shl: {
@@ skipping 10 matching lines @@
       //   use(t3)
       //   t3 = t2
       //   t2 = 0
       // L1:
       //   a.lo = t2
       //   a.hi = t3
       Variable *T_1 = NULL, *T_2 = NULL, *T_3 = NULL;
       Constant *BitTest = Ctx->getConstantInt32(IceType_i32, 0x20);
       Constant *Zero = Ctx->getConstantZero(IceType_i32);
       InstX8632Label *Label = InstX8632Label::create(Func, this);
-      _mov(T_1, Src1Lo, Reg_ecx);
+      _mov(T_1, Src1Lo, RegX8632::Reg_ecx);
       _mov(T_2, Src0Lo);
       _mov(T_3, Src0Hi);
       _shld(T_3, T_2, T_1);
       _shl(T_2, T_1);
       _test(T_1, BitTest);
-      _br(InstX8632Br::Br_e, Label);
+      _br(CondX86::Br_e, Label);
       // Because of the intra-block control flow, we need to fake a use
       // of T_3 to prevent its earlier definition from being dead-code
       // eliminated in the presence of its later definition.
       Context.insert(InstFakeUse::create(Func, T_3));
       _mov(T_3, T_2);
       _mov(T_2, Zero);
       Context.insert(Label);
       _mov(DestLo, T_2);
       _mov(DestHi, T_3);
     } break;
     case InstArithmetic::Lshr: {
       // a=b>>c (unsigned) ==>
       //   t1:ecx = c.lo & 0xff
       //   t2 = b.lo
       //   t3 = b.hi
       //   t2 = shrd t2, t3, t1
       //   t3 = shr t3, t1
       //   test t1, 0x20
       //   je L1
       //   use(t2)
       //   t2 = t3
       //   t3 = 0
       // L1:
       //   a.lo = t2
       //   a.hi = t3
       Variable *T_1 = NULL, *T_2 = NULL, *T_3 = NULL;
       Constant *BitTest = Ctx->getConstantInt32(IceType_i32, 0x20);
       Constant *Zero = Ctx->getConstantZero(IceType_i32);
       InstX8632Label *Label = InstX8632Label::create(Func, this);
-      _mov(T_1, Src1Lo, Reg_ecx);
+      _mov(T_1, Src1Lo, RegX8632::Reg_ecx);
       _mov(T_2, Src0Lo);
       _mov(T_3, Src0Hi);
       _shrd(T_2, T_3, T_1);
       _shr(T_3, T_1);
       _test(T_1, BitTest);
-      _br(InstX8632Br::Br_e, Label);
+      _br(CondX86::Br_e, Label);
       // Because of the intra-block control flow, we need to fake a use
       // of T_3 to prevent its earlier definition from being dead-code
       // eliminated in the presence of its later definition.
       Context.insert(InstFakeUse::create(Func, T_2));
       _mov(T_2, T_3);
       _mov(T_3, Zero);
       Context.insert(Label);
       _mov(DestLo, T_2);
       _mov(DestHi, T_3);
     } break;
     case InstArithmetic::Ashr: {
       // a=b>>c (signed) ==>
       //   t1:ecx = c.lo & 0xff
       //   t2 = b.lo
       //   t3 = b.hi
       //   t2 = shrd t2, t3, t1
       //   t3 = sar t3, t1
       //   test t1, 0x20
       //   je L1
       //   use(t2)
       //   t2 = t3
       //   t3 = sar t3, 0x1f
       // L1:
       //   a.lo = t2
       //   a.hi = t3
       Variable *T_1 = NULL, *T_2 = NULL, *T_3 = NULL;
       Constant *BitTest = Ctx->getConstantInt32(IceType_i32, 0x20);
       Constant *SignExtend = Ctx->getConstantInt32(IceType_i32, 0x1f);
       InstX8632Label *Label = InstX8632Label::create(Func, this);
-      _mov(T_1, Src1Lo, Reg_ecx);
+      _mov(T_1, Src1Lo, RegX8632::Reg_ecx);
       _mov(T_2, Src0Lo);
       _mov(T_3, Src0Hi);
       _shrd(T_2, T_3, T_1);
       _sar(T_3, T_1);
       _test(T_1, BitTest);
-      _br(InstX8632Br::Br_e, Label);
+      _br(CondX86::Br_e, Label);
       // Because of the intra-block control flow, we need to fake a use
       // of T_3 to prevent its earlier definition from being dead-code
       // eliminated in the presence of its later definition.
       Context.insert(InstFakeUse::create(Func, T_2));
       _mov(T_2, T_3);
       _sar(T_3, SignExtend);
       Context.insert(Label);
       _mov(DestLo, T_2);
       _mov(DestHi, T_3);
     } break;
@@ skipping 194 matching lines @@
       break;
     case InstArithmetic::Mul:
       // TODO: Optimize for llvm::isa<Constant>(Src1)
       // TODO: Strength-reduce multiplications by a constant,
       // particularly -1 and powers of 2.  Advanced: use lea to
       // multiply by 3, 5, 9.
       //
       // The 8-bit version of imul only allows the form "imul r/m8"
       // where T must be in eax.
       if (Dest->getType() == IceType_i8)
-        _mov(T, Src0, Reg_eax);
+        _mov(T, Src0, RegX8632::Reg_eax);
       else
         _mov(T, Src0);
       _imul(T, Src1);
       _mov(Dest, T);
       break;
     case InstArithmetic::Shl:
       _mov(T, Src0);
       if (!llvm::isa<Constant>(Src1))
-        Src1 = legalizeToVar(Src1, false, Reg_ecx);
+        Src1 = legalizeToVar(Src1, false, RegX8632::Reg_ecx);
       _shl(T, Src1);
       _mov(Dest, T);
       break;
     case InstArithmetic::Lshr:
       _mov(T, Src0);
       if (!llvm::isa<Constant>(Src1))
-        Src1 = legalizeToVar(Src1, false, Reg_ecx);
+        Src1 = legalizeToVar(Src1, false, RegX8632::Reg_ecx);
       _shr(T, Src1);
       _mov(Dest, T);
       break;
     case InstArithmetic::Ashr:
       _mov(T, Src0);
       if (!llvm::isa<Constant>(Src1))
-        Src1 = legalizeToVar(Src1, false, Reg_ecx);
+        Src1 = legalizeToVar(Src1, false, RegX8632::Reg_ecx);
       _sar(T, Src1);
       _mov(Dest, T);
       break;
     case InstArithmetic::Udiv:
       // div and idiv are the few arithmetic operators that do not allow
       // immediates as the operand.
       Src1 = legalize(Src1, Legal_Reg | Legal_Mem);
       if (Dest->getType() == IceType_i8) {
         Variable *T_ah = NULL;
         Constant *Zero = Ctx->getConstantZero(IceType_i8);
-        _mov(T, Src0, Reg_eax);
-        _mov(T_ah, Zero, Reg_ah);
+        _mov(T, Src0, RegX8632::Reg_eax);
+        _mov(T_ah, Zero, RegX8632::Reg_ah);
         _div(T, Src1, T_ah);
         _mov(Dest, T);
       } else {
         Constant *Zero = Ctx->getConstantZero(IceType_i32);
-        _mov(T, Src0, Reg_eax);
-        _mov(T_edx, Zero, Reg_edx);
+        _mov(T, Src0, RegX8632::Reg_eax);
+        _mov(T_edx, Zero, RegX8632::Reg_edx);
         _div(T, Src1, T_edx);
         _mov(Dest, T);
       }
       break;
     case InstArithmetic::Sdiv:
       Src1 = legalize(Src1, Legal_Reg | Legal_Mem);
       if (Dest->getType() == IceType_i8) {
-        _mov(T, Src0, Reg_eax);
+        _mov(T, Src0, RegX8632::Reg_eax);
         _cbwdq(T, T);
         _idiv(T, Src1, T);
         _mov(Dest, T);
       } else {
-        T_edx = makeReg(IceType_i32, Reg_edx);
-        _mov(T, Src0, Reg_eax);
+        T_edx = makeReg(IceType_i32, RegX8632::Reg_edx);
+        _mov(T, Src0, RegX8632::Reg_eax);
         _cbwdq(T_edx, T);
         _idiv(T, Src1, T_edx);
         _mov(Dest, T);
       }
       break;
     case InstArithmetic::Urem:
       Src1 = legalize(Src1, Legal_Reg | Legal_Mem);
       if (Dest->getType() == IceType_i8) {
         Variable *T_ah = NULL;
         Constant *Zero = Ctx->getConstantZero(IceType_i8);
-        _mov(T, Src0, Reg_eax);
-        _mov(T_ah, Zero, Reg_ah);
+        _mov(T, Src0, RegX8632::Reg_eax);
+        _mov(T_ah, Zero, RegX8632::Reg_ah);
         _div(T_ah, Src1, T);
         _mov(Dest, T_ah);
       } else {
         Constant *Zero = Ctx->getConstantZero(IceType_i32);
-        _mov(T_edx, Zero, Reg_edx);
-        _mov(T, Src0, Reg_eax);
+        _mov(T_edx, Zero, RegX8632::Reg_edx);
+        _mov(T, Src0, RegX8632::Reg_eax);
         _div(T_edx, Src1, T);
         _mov(Dest, T_edx);
       }
       break;
     case InstArithmetic::Srem:
       Src1 = legalize(Src1, Legal_Reg | Legal_Mem);
       if (Dest->getType() == IceType_i8) {
-        Variable *T_ah = makeReg(IceType_i8, Reg_ah);
-        _mov(T, Src0, Reg_eax);
+        Variable *T_ah = makeReg(IceType_i8, RegX8632::Reg_ah);
+        _mov(T, Src0, RegX8632::Reg_eax);
         _cbwdq(T, T);
         Context.insert(InstFakeDef::create(Func, T_ah));
         _idiv(T_ah, Src1, T);
         _mov(Dest, T_ah);
       } else {
-        T_edx = makeReg(IceType_i32, Reg_edx);
-        _mov(T, Src0, Reg_eax);
+        T_edx = makeReg(IceType_i32, RegX8632::Reg_edx);
+        _mov(T, Src0, RegX8632::Reg_eax);
         _cbwdq(T_edx, T);
         _idiv(T_edx, Src1, T);
         _mov(Dest, T_edx);
       }
       break;
     case InstArithmetic::Fadd:
       _mov(T, Src0);
       _addss(T, Src1);
       _mov(Dest, T);
       break;
@@ skipping 51 matching lines @@
   }
 }
 
 void TargetX8632::lowerBr(const InstBr *Inst) {
   if (Inst->isUnconditional()) {
     _br(Inst->getTargetUnconditional());
   } else {
     Operand *Src0 = legalize(Inst->getCondition(), Legal_Reg | Legal_Mem);
     Constant *Zero = Ctx->getConstantZero(IceType_i32);
     _cmp(Src0, Zero);
-    _br(InstX8632Br::Br_ne, Inst->getTargetTrue(), Inst->getTargetFalse());
+    _br(CondX86::Br_ne, Inst->getTargetTrue(), Inst->getTargetFalse());
   }
 }
 
 void TargetX8632::lowerCall(const InstCall *Instr) {
   // x86-32 calling convention:
   //
   // * At the point before the call, the stack must be aligned to 16
   // bytes.
   //
   // * The first four arguments of vector type, regardless of their
@@ skipping 25 matching lines @@
     // The PNaCl ABI requires the width of arguments to be at least 32 bits.
     assert(Ty == IceType_i32 || Ty == IceType_f32 || Ty == IceType_i64 ||
            Ty == IceType_f64 || isVectorType(Ty));
     if (isVectorType(Ty) && XmmArgs.size() < X86_MAX_XMM_ARGS) {
       XmmArgs.push_back(Arg);
     } else {
       StackArgs.push_back(Arg);
       if (isVectorType(Arg->getType())) {
         ParameterAreaSizeBytes = applyStackAlignment(ParameterAreaSizeBytes);
       }
-      Variable *esp = Func->getTarget()->getPhysicalRegister(Reg_esp);
+      Variable *esp = Func->getTarget()->getPhysicalRegister(RegX8632::Reg_esp);
       Constant *Loc =
           Ctx->getConstantInt32(IceType_i32, ParameterAreaSizeBytes);
       StackArgLocations.push_back(OperandX8632Mem::create(Func, Ty, esp, Loc));
       ParameterAreaSizeBytes += typeWidthInBytesOnStack(Arg->getType());
     }
   }
 
   // Adjust the parameter area so that the stack is aligned.  It is
   // assumed that the stack is already aligned at the start of the
   // calling sequence.
@@ skipping 21 matching lines @@
   // Copy arguments to be passed in registers to the appropriate
   // registers.
   // TODO: Investigate the impact of lowering arguments passed in
   // registers after lowering stack arguments as opposed to the other
   // way around.  Lowering register arguments after stack arguments may
   // reduce register pressure.  On the other hand, lowering register
   // arguments first (before stack arguments) may result in more compact
   // code, as the memory operand displacements may end up being smaller
   // before any stack adjustment is done.
   for (SizeT i = 0, NumXmmArgs = XmmArgs.size(); i < NumXmmArgs; ++i) {
-    Variable *Reg = legalizeToVar(XmmArgs[i], false, Reg_xmm0 + i);
+    Variable *Reg = legalizeToVar(XmmArgs[i], false, RegX8632::Reg_xmm0 + i);
     // Generate a FakeUse of register arguments so that they do not get
     // dead code eliminated as a result of the FakeKill of scratch
     // registers after the call.
     Context.insert(InstFakeUse::create(Func, Reg));
   }
   // Generate the call instruction.  Assign its result to a temporary
   // with high register allocation weight.
   Variable *Dest = Instr->getDest();
   // ReturnReg doubles as ReturnRegLo as necessary.
   Variable *ReturnReg = NULL;
   Variable *ReturnRegHi = NULL;
   if (Dest) {
     switch (Dest->getType()) {
     case IceType_NUM:
       llvm_unreachable("Invalid Call dest type");
       break;
     case IceType_void:
       break;
     case IceType_i1:
     case IceType_i8:
     case IceType_i16:
     case IceType_i32:
-      ReturnReg = makeReg(Dest->getType(), Reg_eax);
+      ReturnReg = makeReg(Dest->getType(), RegX8632::Reg_eax);
       break;
     case IceType_i64:
-      ReturnReg = makeReg(IceType_i32, Reg_eax);
-      ReturnRegHi = makeReg(IceType_i32, Reg_edx);
+      ReturnReg = makeReg(IceType_i32, RegX8632::Reg_eax);
+      ReturnRegHi = makeReg(IceType_i32, RegX8632::Reg_edx);
       break;
     case IceType_f32:
     case IceType_f64:
       // Leave ReturnReg==ReturnRegHi==NULL, and capture the result with
       // the fstp instruction.
       break;
     case IceType_v4i1:
     case IceType_v8i1:
     case IceType_v16i1:
     case IceType_v16i8:
     case IceType_v8i16:
     case IceType_v4i32:
     case IceType_v4f32:
-      ReturnReg = makeReg(Dest->getType(), Reg_xmm0);
+      ReturnReg = makeReg(Dest->getType(), RegX8632::Reg_xmm0);
       break;
     }
   }
   // TODO(stichnot): LEAHACK: remove Legal_All (and use default) once
   // a proper emitter is used.
   Operand *CallTarget = legalize(Instr->getCallTarget(), Legal_All);
   Inst *NewCall = InstX8632Call::create(Func, ReturnReg, CallTarget);
   Context.insert(NewCall);
   if (ReturnRegHi)
     Context.insert(InstFakeDef::create(Func, ReturnRegHi));
 
   // Add the appropriate offset to esp.  The call instruction takes care
   // of resetting the stack offset during emission.
   if (ParameterAreaSizeBytes) {
-    Variable *esp = Func->getTarget()->getPhysicalRegister(Reg_esp);
+    Variable *esp = Func->getTarget()->getPhysicalRegister(RegX8632::Reg_esp);
     _add(esp, Ctx->getConstantInt32(IceType_i32, ParameterAreaSizeBytes));
   }
 
   // Insert a register-kill pseudo instruction.
   VarList KilledRegs;
   for (SizeT i = 0; i < ScratchRegs.size(); ++i) {
     if (ScratchRegs[i])
       KilledRegs.push_back(Func->getTarget()->getPhysicalRegister(i));
   }
   Context.insert(InstFakeKill::create(Func, KilledRegs, NewCall));
@@ skipping 579 matching lines @@
       // makeVectorOfOnes() requires an integer vector type.
       T = makeVectorOfMinusOnes(IceType_v4i32);
     } else if (Condition == InstFcmp::False) {
       T = makeVectorOfZeros(Dest->getType());
     } else {
       Operand *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem);
       Operand *Src1RM = legalize(Src1, Legal_Reg | Legal_Mem);
 
       switch (Condition) {
       default: {
-        InstX8632Cmpps::CmppsCond Predicate = TableFcmp[Index].Predicate;
-        assert(Predicate != InstX8632Cmpps::Cmpps_Invalid);
+        CondX86::CmppsCond Predicate = TableFcmp[Index].Predicate;
+        assert(Predicate != CondX86::Cmpps_Invalid);
         T = makeReg(Src0RM->getType());
         _movp(T, Src0RM);
         _cmpps(T, Src1RM, Predicate);
       } break;
       case InstFcmp::One: {
         // Check both unequal and ordered.
         T = makeReg(Src0RM->getType());
         Variable *T2 = makeReg(Src0RM->getType());
         _movp(T, Src0RM);
-        _cmpps(T, Src1RM, InstX8632Cmpps::Cmpps_neq);
+        _cmpps(T, Src1RM, CondX86::Cmpps_neq);
         _movp(T2, Src0RM);
-        _cmpps(T2, Src1RM, InstX8632Cmpps::Cmpps_ord);
+        _cmpps(T2, Src1RM, CondX86::Cmpps_ord);
         _pand(T, T2);
       } break;
       case InstFcmp::Ueq: {
         // Check both equal or unordered.
         T = makeReg(Src0RM->getType());
         Variable *T2 = makeReg(Src0RM->getType());
         _movp(T, Src0RM);
-        _cmpps(T, Src1RM, InstX8632Cmpps::Cmpps_eq);
+        _cmpps(T, Src1RM, CondX86::Cmpps_eq);
         _movp(T2, Src0RM);
-        _cmpps(T2, Src1RM, InstX8632Cmpps::Cmpps_unord);
+        _cmpps(T2, Src1RM, CondX86::Cmpps_unord);
         _por(T, T2);
       } break;
       }
     }
 
     _movp(Dest, T);
     eliminateNextVectorSextInstruction(Dest);
     return;
   }
 
   // Lowering a = fcmp cond, b, c
   //   ucomiss b, c       /* only if C1 != Br_None */
   //                      /* but swap b,c order if SwapOperands==true */
   //   mov a, <default>
   //   j<C1> label        /* only if C1 != Br_None */
   //   j<C2> label        /* only if C2 != Br_None */
   //   FakeUse(a)         /* only if C1 != Br_None */
   //   mov a, !<default>  /* only if C1 != Br_None */
   //   label:             /* only if C1 != Br_None */
   InstFcmp::FCond Condition = Inst->getCondition();
   size_t Index = static_cast<size_t>(Condition);
   assert(Index < TableFcmpSize);
   if (TableFcmp[Index].SwapScalarOperands) {
     Operand *Tmp = Src0;
     Src0 = Src1;
     Src1 = Tmp;
   }
-  bool HasC1 = (TableFcmp[Index].C1 != InstX8632Br::Br_None);
-  bool HasC2 = (TableFcmp[Index].C2 != InstX8632Br::Br_None);
+  bool HasC1 = (TableFcmp[Index].C1 != CondX86::Br_None);
+  bool HasC2 = (TableFcmp[Index].C2 != CondX86::Br_None);
   if (HasC1) {
     Src0 = legalize(Src0);
     Operand *Src1RM = legalize(Src1, Legal_Reg | Legal_Mem);
     Variable *T = NULL;
     _mov(T, Src0);
     _ucomiss(T, Src1RM);
   }
   Constant *Default =
       Ctx->getConstantInt32(IceType_i32, TableFcmp[Index].Default);
   _mov(Dest, Default);
@@ skipping 152 matching lines @@
     size_t Index = static_cast<size_t>(Condition);
     assert(Index < TableIcmp64Size);
     Operand *Src0LoRM = legalize(loOperand(Src0), Legal_Reg | Legal_Mem);
     Operand *Src0HiRM = legalize(hiOperand(Src0), Legal_Reg | Legal_Mem);
     Operand *Src1LoRI = legalize(loOperand(Src1), Legal_Reg | Legal_Imm);
     Operand *Src1HiRI = legalize(hiOperand(Src1), Legal_Reg | Legal_Imm);
     if (Condition == InstIcmp::Eq || Condition == InstIcmp::Ne) {
       InstX8632Label *Label = InstX8632Label::create(Func, this);
       _mov(Dest, (Condition == InstIcmp::Eq ? Zero : One));
       _cmp(Src0LoRM, Src1LoRI);
-      _br(InstX8632Br::Br_ne, Label);
+      _br(CondX86::Br_ne, Label);
       _cmp(Src0HiRM, Src1HiRI);
-      _br(InstX8632Br::Br_ne, Label);
+      _br(CondX86::Br_ne, Label);
       Context.insert(InstFakeUse::create(Func, Dest));
       _mov(Dest, (Condition == InstIcmp::Eq ? One : Zero));
       Context.insert(Label);
     } else {
       InstX8632Label *LabelFalse = InstX8632Label::create(Func, this);
       InstX8632Label *LabelTrue = InstX8632Label::create(Func, this);
       _mov(Dest, One);
       _cmp(Src0HiRM, Src1HiRI);
       _br(TableIcmp64[Index].C1, LabelTrue);
       _br(TableIcmp64[Index].C2, LabelFalse);
@@ skipping 432 matching lines @@
   }
   case Intrinsics::Sqrt: {
     Operand *Src = legalize(Instr->getArg(0));
     Variable *Dest = Instr->getDest();
     Variable *T = makeReg(Dest->getType());
     _sqrtss(T, Src);
     _mov(Dest, T);
     return;
   }
   case Intrinsics::Stacksave: {
-    Variable *esp = Func->getTarget()->getPhysicalRegister(Reg_esp);
+    Variable *esp = Func->getTarget()->getPhysicalRegister(RegX8632::Reg_esp);
     Variable *Dest = Instr->getDest();
     _mov(Dest, esp);
     return;
   }
   case Intrinsics::Stackrestore: {
-    Variable *esp = Func->getTarget()->getPhysicalRegister(Reg_esp);
+    Variable *esp = Func->getTarget()->getPhysicalRegister(RegX8632::Reg_esp);
     _mov(esp, Instr->getArg(0));
     return;
   }
   case Intrinsics::Trap:
     _ud2();
     return;
   case Intrinsics::UnknownIntrinsic:
     Func->setError("Should not be lowering UnknownIntrinsic");
     return;
   }
   return;
 }
 
 void TargetX8632::lowerAtomicCmpxchg(Variable *DestPrev, Operand *Ptr,
                                      Operand *Expected, Operand *Desired) {
   if (Expected->getType() == IceType_i64) {
     // Reserve the pre-colored registers first, before adding any more
     // infinite-weight variables from FormMemoryOperand's legalization.
-    Variable *T_edx = makeReg(IceType_i32, Reg_edx);
-    Variable *T_eax = makeReg(IceType_i32, Reg_eax);
-    Variable *T_ecx = makeReg(IceType_i32, Reg_ecx);
-    Variable *T_ebx = makeReg(IceType_i32, Reg_ebx);
+    Variable *T_edx = makeReg(IceType_i32, RegX8632::Reg_edx);
+    Variable *T_eax = makeReg(IceType_i32, RegX8632::Reg_eax);
+    Variable *T_ecx = makeReg(IceType_i32, RegX8632::Reg_ecx);
+    Variable *T_ebx = makeReg(IceType_i32, RegX8632::Reg_ebx);
     _mov(T_eax, loOperand(Expected));
     _mov(T_edx, hiOperand(Expected));
     _mov(T_ebx, loOperand(Desired));
     _mov(T_ecx, hiOperand(Desired));
     OperandX8632Mem *Addr = FormMemoryOperand(Ptr, Expected->getType());
     const bool Locked = true;
     _cmpxchg8b(Addr, T_edx, T_eax, T_ecx, T_ebx, Locked);
     Variable *DestLo = llvm::cast<Variable>(loOperand(DestPrev));
     Variable *DestHi = llvm::cast<Variable>(hiOperand(DestPrev));
     _mov(DestLo, T_eax);
     _mov(DestHi, T_edx);
     return;
   }
-  Variable *T_eax = makeReg(Expected->getType(), Reg_eax);
+  Variable *T_eax = makeReg(Expected->getType(), RegX8632::Reg_eax);
   _mov(T_eax, Expected);
   OperandX8632Mem *Addr = FormMemoryOperand(Ptr, Expected->getType());
   Variable *DesiredReg = legalizeToVar(Desired);
   const bool Locked = true;
   _cmpxchg(Addr, T_eax, DesiredReg, Locked);
   _mov(DestPrev, T_eax);
 }
 
 bool TargetX8632::tryOptimizedCmpxchgCmpBr(Variable *Dest, Operand *PtrToMem,
                                            Operand *Expected,
@@ skipping 48 matching lines @@
           NextBr->isLastUse(NextCmp->getDest())) {
         lowerAtomicCmpxchg(Dest, PtrToMem, Expected, Desired);
         for (size_t i = 0; i < PhiAssigns.size(); ++i) {
           // Lower the phi assignments now, before the branch (same placement
           // as before).
           InstAssign *PhiAssign = PhiAssigns[i];
           PhiAssign->setDeleted();
           lowerAssign(PhiAssign);
           Context.advanceNext();
         }
-        _br(InstX8632::Br_e, NextBr->getTargetTrue(), NextBr->getTargetFalse());
+        _br(CondX86::Br_e, NextBr->getTargetTrue(), NextBr->getTargetFalse());
         // Skip over the old compare and branch, by deleting them.
         NextCmp->setDeleted();
         NextBr->setDeleted();
         Context.advanceNext();
         Context.advanceNext();
         return true;
       }
     }
   }
   return false;
@@ skipping 106 matching lines @@
   //   mov     <reg>, eax
   //   op      <reg>, [desired_adj]
   //   lock cmpxchg [ptr], <reg>
   //   jne     .LABEL
   //   mov     <dest>, eax
   //
   // If Op_{Lo,Hi} are NULL, then just copy the value.
   Val = legalize(Val);
   Type Ty = Val->getType();
   if (Ty == IceType_i64) {
-    Variable *T_edx = makeReg(IceType_i32, Reg_edx);
-    Variable *T_eax = makeReg(IceType_i32, Reg_eax);
+    Variable *T_edx = makeReg(IceType_i32, RegX8632::Reg_edx);
+    Variable *T_eax = makeReg(IceType_i32, RegX8632::Reg_eax);
     OperandX8632Mem *Addr = FormMemoryOperand(Ptr, Ty);
     _mov(T_eax, loOperand(Addr));
     _mov(T_edx, hiOperand(Addr));
-    Variable *T_ecx = makeReg(IceType_i32, Reg_ecx);
-    Variable *T_ebx = makeReg(IceType_i32, Reg_ebx);
+    Variable *T_ecx = makeReg(IceType_i32, RegX8632::Reg_ecx);
+    Variable *T_ebx = makeReg(IceType_i32, RegX8632::Reg_ebx);
     InstX8632Label *Label = InstX8632Label::create(Func, this);
     const bool IsXchg8b = Op_Lo == NULL && Op_Hi == NULL;
     if (!IsXchg8b) {
       Context.insert(Label);
       _mov(T_ebx, T_eax);
       (this->*Op_Lo)(T_ebx, loOperand(Val));
       _mov(T_ecx, T_edx);
       (this->*Op_Hi)(T_ecx, hiOperand(Val));
     } else {
       // This is for xchg, which doesn't need an actual Op_Lo/Op_Hi.
       // It just needs the Val loaded into ebx and ecx.
       // That can also be done before the loop.
       _mov(T_ebx, loOperand(Val));
       _mov(T_ecx, hiOperand(Val));
       Context.insert(Label);
     }
     const bool Locked = true;
     _cmpxchg8b(Addr, T_edx, T_eax, T_ecx, T_ebx, Locked);
-    _br(InstX8632Br::Br_ne, Label);
+    _br(CondX86::Br_ne, Label);
     if (!IsXchg8b) {
       // If Val is a variable, model the extended live range of Val through
       // the end of the loop, since it will be re-used by the loop.
       if (Variable *ValVar = llvm::dyn_cast<Variable>(Val)) {
         Variable *ValLo = llvm::cast<Variable>(loOperand(ValVar));
         Variable *ValHi = llvm::cast<Variable>(hiOperand(ValVar));
         Context.insert(InstFakeUse::create(Func, ValLo));
         Context.insert(InstFakeUse::create(Func, ValHi));
       }
     } else {
       // For xchg, the loop is slightly smaller and ebx/ecx are used.
       Context.insert(InstFakeUse::create(Func, T_ebx));
       Context.insert(InstFakeUse::create(Func, T_ecx));
     }
     // The address base is also reused in the loop.
     Context.insert(InstFakeUse::create(Func, Addr->getBase()));
     Variable *DestLo = llvm::cast<Variable>(loOperand(Dest));
     Variable *DestHi = llvm::cast<Variable>(hiOperand(Dest));
     _mov(DestLo, T_eax);
     _mov(DestHi, T_edx);
     return;
   }
   OperandX8632Mem *Addr = FormMemoryOperand(Ptr, Ty);
-  Variable *T_eax = makeReg(Ty, Reg_eax);
+  Variable *T_eax = makeReg(Ty, RegX8632::Reg_eax);
   _mov(T_eax, Addr);
   InstX8632Label *Label = InstX8632Label::create(Func, this);
   Context.insert(Label);
   // We want to pick a different register for T than Eax, so don't use
   // _mov(T == NULL, T_eax).
   Variable *T = makeReg(Ty);
   _mov(T, T_eax);
   (this->*Op_Lo)(T, Val);
   const bool Locked = true;
   _cmpxchg(Addr, T_eax, T, Locked);
-  _br(InstX8632Br::Br_ne, Label);
+  _br(CondX86::Br_ne, Label);
   // If Val is a variable, model the extended live range of Val through
   // the end of the loop, since it will be re-used by the loop.
   if (Variable *ValVar = llvm::dyn_cast<Variable>(Val)) {
     Context.insert(InstFakeUse::create(Func, ValVar));
   }
   // The address base is also reused in the loop.
   Context.insert(InstFakeUse::create(Func, Addr->getBase()));
   _mov(Dest, T_eax);
 }
 
@@ skipping 40 matching lines @@
   }
   Variable *T_Dest = makeReg(IceType_i32);
   Constant *ThirtyTwo = Ctx->getConstantInt32(IceType_i32, 32);
   Constant *ThirtyOne = Ctx->getConstantInt32(IceType_i32, 31);
   if (Cttz) {
     _mov(T_Dest, ThirtyTwo);
   } else {
     Constant *SixtyThree = Ctx->getConstantInt32(IceType_i32, 63);
     _mov(T_Dest, SixtyThree);
   }
-  _cmov(T_Dest, T, InstX8632::Br_ne);
+  _cmov(T_Dest, T, CondX86::Br_ne);
   if (!Cttz) {
     _xor(T_Dest, ThirtyOne);
   }
   if (Ty == IceType_i32) {
     _mov(Dest, T_Dest);
     return;
   }
   _add(T_Dest, ThirtyTwo);
   Variable *DestLo = llvm::cast<Variable>(loOperand(Dest));
   Variable *DestHi = llvm::cast<Variable>(hiOperand(Dest));
   // Will be using "test" on this, so we need a registerized variable.
   Variable *SecondVar = legalizeToVar(SecondVal);
   Variable *T_Dest2 = makeReg(IceType_i32);
   if (Cttz) {
     _bsf(T_Dest2, SecondVar);
   } else {
     _bsr(T_Dest2, SecondVar);
     _xor(T_Dest2, ThirtyOne);
   }
   _test(SecondVar, SecondVar);
-  _cmov(T_Dest2, T_Dest, InstX8632::Br_e);
+  _cmov(T_Dest2, T_Dest, CondX86::Br_e);
   _mov(DestLo, T_Dest2);
   _mov(DestHi, Ctx->getConstantZero(IceType_i32));
 }
 
 namespace {
 
 bool isAdd(const Inst *Inst) {
   if (const InstArithmetic *Arith =
           llvm::dyn_cast_or_null<const InstArithmetic>(Inst)) {
     return (Arith->getOp() == InstArithmetic::Add);
@@ skipping 306 matching lines @@
 
 void TargetX8632::lowerPhi(const InstPhi * /*Inst*/) {
   Func->setError("Phi found in regular instruction list");
 }
 
 void TargetX8632::lowerRet(const InstRet *Inst) {
   Variable *Reg = NULL;
   if (Inst->hasRetValue()) {
     Operand *Src0 = legalize(Inst->getRetValue());
     if (Src0->getType() == IceType_i64) {
-      Variable *eax = legalizeToVar(loOperand(Src0), false, Reg_eax);
-      Variable *edx = legalizeToVar(hiOperand(Src0), false, Reg_edx);
+      Variable *eax = legalizeToVar(loOperand(Src0), false, RegX8632::Reg_eax);
+      Variable *edx = legalizeToVar(hiOperand(Src0), false, RegX8632::Reg_edx);
       Reg = eax;
       Context.insert(InstFakeUse::create(Func, edx));
     } else if (Src0->getType() == IceType_f32 ||
                Src0->getType() == IceType_f64) {
       _fld(Src0);
     } else if (isVectorType(Src0->getType())) {
-      Reg = legalizeToVar(Src0, false, Reg_xmm0);
+      Reg = legalizeToVar(Src0, false, RegX8632::Reg_xmm0);
     } else {
-      _mov(Reg, Src0, Reg_eax);
+      _mov(Reg, Src0, RegX8632::Reg_eax);
     }
   }
   _ret(Reg);
   // Add a fake use of esp to make sure esp stays alive for the entire
   // function.  Otherwise post-call esp adjustments get dead-code
   // eliminated.  TODO: Are there more places where the fake use
   // should be inserted?  E.g. "void f(int n){while(1) g(n);}" may not
   // have a ret instruction.
-  Variable *esp = Func->getTarget()->getPhysicalRegister(Reg_esp);
+  Variable *esp = Func->getTarget()->getPhysicalRegister(RegX8632::Reg_esp);
   Context.insert(InstFakeUse::create(Func, esp));
 }
 
 void TargetX8632::lowerSelect(const InstSelect *Inst) {
   Variable *Dest = Inst->getDest();
   Operand *SrcT = Inst->getTrueOperand();
   Operand *SrcF = Inst->getFalseOperand();
   Operand *Condition = Inst->getCondition();
 
   if (isVectorType(Dest->getType())) {
     Type SrcTy = SrcT->getType();
     Variable *T = makeReg(SrcTy);
     Operand *SrcTRM = legalize(SrcT, Legal_Reg | Legal_Mem);
     Operand *SrcFRM = legalize(SrcF, Legal_Reg | Legal_Mem);
     if (InstructionSet >= SSE4_1) {
       // TODO(wala): If the condition operand is a constant, use blendps
       // or pblendw.
       //
       // Use blendvps or pblendvb to implement select.
       if (SrcTy == IceType_v4i1 || SrcTy == IceType_v4i32 ||
           SrcTy == IceType_v4f32) {
         Operand *ConditionRM = legalize(Condition, Legal_Reg | Legal_Mem);
-        Variable *xmm0 = makeReg(IceType_v4i32, Reg_xmm0);
+        Variable *xmm0 = makeReg(IceType_v4i32, RegX8632::Reg_xmm0);
         _movp(xmm0, ConditionRM);
         _psll(xmm0, Ctx->getConstantInt32(IceType_i8, 31));
         _movp(T, SrcFRM);
         _blendvps(T, SrcTRM, xmm0);
         _movp(Dest, T);
       } else {
         assert(typeNumElements(SrcTy) == 8 || typeNumElements(SrcTy) == 16);
         Type SignExtTy = Condition->getType() == IceType_v8i1 ? IceType_v8i16
             : IceType_v16i8;
-        Variable *xmm0 = makeReg(SignExtTy, Reg_xmm0);
+        Variable *xmm0 = makeReg(SignExtTy, RegX8632::Reg_xmm0);
         lowerCast(InstCast::create(Func, InstCast::Sext, xmm0, Condition));
         _movp(T, SrcFRM);
         _pblendvb(T, SrcTRM, xmm0);
         _movp(Dest, T);
       }
       return;
     }
     // Lower select without SSE4.1:
     // a=d?b:c ==>
     //   if elementtype(d) != i1:
@@ skipping 27 matching lines @@
   InstX8632Label *Label = InstX8632Label::create(Func, this);
 
   if (Dest->getType() == IceType_i64) {
     Variable *DestLo = llvm::cast<Variable>(loOperand(Dest));
     Variable *DestHi = llvm::cast<Variable>(hiOperand(Dest));
     Operand *SrcLoRI = legalize(loOperand(SrcT), Legal_Reg | Legal_Imm, true);
     Operand *SrcHiRI = legalize(hiOperand(SrcT), Legal_Reg | Legal_Imm, true);
     _cmp(ConditionRM, Zero);
     _mov(DestLo, SrcLoRI);
     _mov(DestHi, SrcHiRI);
-    _br(InstX8632Br::Br_ne, Label);
+    _br(CondX86::Br_ne, Label);
     Context.insert(InstFakeUse::create(Func, DestLo));
     Context.insert(InstFakeUse::create(Func, DestHi));
     Operand *SrcFLo = loOperand(SrcF);
     Operand *SrcFHi = hiOperand(SrcF);
     SrcLoRI = legalize(SrcFLo, Legal_Reg | Legal_Imm, true);
     SrcHiRI = legalize(SrcFHi, Legal_Reg | Legal_Imm, true);
     _mov(DestLo, SrcLoRI);
     _mov(DestHi, SrcHiRI);
   } else {
     _cmp(ConditionRM, Zero);
     SrcT = legalize(SrcT, Legal_Reg | Legal_Imm, true);
     _mov(Dest, SrcT);
-    _br(InstX8632Br::Br_ne, Label);
+    _br(CondX86::Br_ne, Label);
     Context.insert(InstFakeUse::create(Func, Dest));
     SrcF = legalize(SrcF, Legal_Reg | Legal_Imm, true);
     _mov(Dest, SrcF);
   }
 
   Context.insert(Label);
 }
 
 void TargetX8632::lowerStore(const InstStore *Inst) {
   Operand *Value = Inst->getData();
@@ skipping 47 matching lines @@
   // OK, we'll be slightly less naive by forcing Src into a physical
   // register if there are 2 or more uses.
   if (NumCases >= 2)
     Src0 = legalizeToVar(Src0, true);
   else
     Src0 = legalize(Src0, Legal_Reg | Legal_Mem, true);
   for (SizeT I = 0; I < NumCases; ++I) {
     // TODO(stichnot): Correct lowering for IceType_i64.
     Constant *Value = Ctx->getConstantInt32(IceType_i32, Inst->getValue(I));
     _cmp(Src0, Value);
-    _br(InstX8632Br::Br_e, Inst->getLabel(I));
+    _br(CondX86::Br_e, Inst->getLabel(I));
   }
 
   _br(Inst->getLabelDefault());
 }
 
 void TargetX8632::scalarizeArithmetic(InstArithmetic::OpKind Kind,
                                       Variable *Dest, Operand *Src0,
                                       Operand *Src1) {
   assert(isVectorType(Dest->getType()));
   Type Ty = Dest->getType();
@@ skipping 487 matching lines @@
     Str << "\t.align\t" << Align << "\n";
     Str << MangledName << ":\n";
     for (SizeT i = 0; i < Size; ++i) {
       Str << "\t.byte\t" << (((unsigned)Data[i]) & 0xff) << "\n";
     }
     Str << "\t.size\t" << MangledName << ", " << Size << "\n";
   }
 }
 
 } // end of namespace Ice