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Issue 58003003: Impelments IfThenElse instruction for ARM and MIPS. (Closed) Base URL: http://dart.googlecode.com/svn/branches/bleeding_edge/dart/
Patch Set: Created 7 years, 1 month ago
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1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
2 // for details. All rights reserved. Use of this source code is governed by a 2 // for details. All rights reserved. Use of this source code is governed by a
3 // BSD-style license that can be found in the LICENSE file. 3 // BSD-style license that can be found in the LICENSE file.
4 4
5 #include "vm/globals.h" 5 #include "vm/globals.h"
6 #if defined(TARGET_ARCH_ARM) 6 #if defined(TARGET_ARCH_ARM)
7 7
8 #include "vm/assembler.h" 8 #include "vm/assembler.h"
9 #include "vm/longjump.h" 9 #include "vm/longjump.h"
10 #include "vm/runtime_entry.h" 10 #include "vm/runtime_entry.h"
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2411 const uint16_t value_high = Utils::High16Bits(value); 2411 const uint16_t value_high = Utils::High16Bits(value);
2412 if (value_high != 0) { 2412 if (value_high != 0) {
2413 movt(IP, value_high, cond); 2413 movt(IP, value_high, cond);
2414 } 2414 }
2415 adc(rd, rn, ShifterOperand(IP), cond); 2415 adc(rd, rn, ShifterOperand(IP), cond);
2416 } 2416 }
2417 } 2417 }
2418 } 2418 }
2419 2419
2420 2420
2421 void Assembler::AndImmediate(Register rd, Register rs, int32_t imm,
2422 Condition cond) {
2423 ShifterOperand op;
2424 if (ShifterOperand::CanHold(imm, &op)) {
2425 and_(rd, rs, ShifterOperand(op), cond);
2426 } else {
2427 LoadImmediate(TMP, imm, cond);
2428 and_(rd, rs, ShifterOperand(TMP), cond);
2429 }
2430 }
2431
2432
2421 void Assembler::CompareImmediate(Register rn, int32_t value, Condition cond) { 2433 void Assembler::CompareImmediate(Register rn, int32_t value, Condition cond) {
2422 ShifterOperand shifter_op; 2434 ShifterOperand shifter_op;
2423 if (ShifterOperand::CanHold(value, &shifter_op)) { 2435 if (ShifterOperand::CanHold(value, &shifter_op)) {
2424 cmp(rn, shifter_op, cond); 2436 cmp(rn, shifter_op, cond);
2425 } else { 2437 } else {
2426 ASSERT(rn != IP); 2438 ASSERT(rn != IP);
2427 LoadImmediate(IP, value, cond); 2439 LoadImmediate(IP, value, cond);
2428 cmp(rn, ShifterOperand(IP), cond); 2440 cmp(rn, ShifterOperand(IP), cond);
2429 } 2441 }
2430 } 2442 }
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2740 2752
2741 const char* Assembler::FpuRegisterName(FpuRegister reg) { 2753 const char* Assembler::FpuRegisterName(FpuRegister reg) {
2742 ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters)); 2754 ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters));
2743 return fpu_reg_names[reg]; 2755 return fpu_reg_names[reg];
2744 } 2756 }
2745 2757
2746 } // namespace dart 2758 } // namespace dart
2747 2759
2748 #endif // defined TARGET_ARCH_ARM 2760 #endif // defined TARGET_ARCH_ARM
2749 2761
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