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| 1 ; Test parsing NaCl atomic instructions. |
| 2 |
| 3 ; RUN: llvm-as < %s | pnacl-freeze -allow-local-symbol-tables \ |
| 4 ; RUN: | %llvm2ice -notranslate -verbose=inst -build-on-read \ |
| 5 ; RUN: -allow-pnacl-reader-error-recovery \ |
| 6 ; RUN: -allow-local-symbol-tables \ |
| 7 ; RUN: | FileCheck %s |
| 8 |
| 9 declare i8 @llvm.nacl.atomic.load.i8(i8*, i32) |
| 10 declare i16 @llvm.nacl.atomic.load.i16(i16*, i32) |
| 11 declare i32 @llvm.nacl.atomic.load.i32(i32*, i32) |
| 12 declare i64 @llvm.nacl.atomic.load.i64(i64*, i32) |
| 13 declare void @llvm.nacl.atomic.store.i8(i8, i8*, i32) |
| 14 declare void @llvm.nacl.atomic.store.i16(i16, i16*, i32) |
| 15 declare void @llvm.nacl.atomic.store.i32(i32, i32*, i32) |
| 16 declare void @llvm.nacl.atomic.store.i64(i64, i64*, i32) |
| 17 declare i8 @llvm.nacl.atomic.rmw.i8(i32, i8*, i8, i32) |
| 18 declare i16 @llvm.nacl.atomic.rmw.i16(i32, i16*, i16, i32) |
| 19 declare i32 @llvm.nacl.atomic.rmw.i32(i32, i32*, i32, i32) |
| 20 declare i64 @llvm.nacl.atomic.rmw.i64(i32, i64*, i64, i32) |
| 21 declare i8 @llvm.nacl.atomic.cmpxchg.i8(i8*, i8, i8, i32, i32) |
| 22 declare i16 @llvm.nacl.atomic.cmpxchg.i16(i16*, i16, i16, i32, i32) |
| 23 declare i32 @llvm.nacl.atomic.cmpxchg.i32(i32*, i32, i32, i32, i32) |
| 24 declare i64 @llvm.nacl.atomic.cmpxchg.i64(i64*, i64, i64, i32, i32) |
| 25 declare void @llvm.nacl.atomic.fence(i32) |
| 26 declare void @llvm.nacl.atomic.fence.all() |
| 27 declare i1 @llvm.nacl.atomic.is.lock.free(i32, i8*) |
| 28 |
| 29 ;;; Load |
| 30 |
| 31 define i32 @test_atomic_load_8(i32 %iptr) { |
| 32 entry: |
| 33 %ptr = inttoptr i32 %iptr to i8* |
| 34 ; parameter value "6" is for the sequential consistency memory order. |
| 35 %i = call i8 @llvm.nacl.atomic.load.i8(i8* %ptr, i32 6) |
| 36 %r = zext i8 %i to i32 |
| 37 ret i32 %r |
| 38 } |
| 39 |
| 40 ; CHECK: define i32 @test_atomic_load_8(i32 %iptr) { |
| 41 ; CHECK-NEXT: entry: |
| 42 ; CHECK-NEXT: %i = call i8 @llvm.nacl.atomic.load.i8(i32 %iptr, i32 6) |
| 43 ; CHECK-NEXT: %r = zext i8 %i to i32 |
| 44 ; CHECK-NEXT: ret i32 %r |
| 45 ; CHECK-NEXT: } |
| 46 |
| 47 define i32 @test_atomic_load_16(i32 %iptr) { |
| 48 entry: |
| 49 %ptr = inttoptr i32 %iptr to i16* |
| 50 %i = call i16 @llvm.nacl.atomic.load.i16(i16* %ptr, i32 6) |
| 51 %r = zext i16 %i to i32 |
| 52 ret i32 %r |
| 53 } |
| 54 |
| 55 ; CHECK-NEXT: define i32 @test_atomic_load_16(i32 %iptr) { |
| 56 ; CHECK-NEXT: entry: |
| 57 ; CHECK-NEXT: %i = call i16 @llvm.nacl.atomic.load.i16(i32 %iptr, i32 6) |
| 58 ; CHECK-NEXT: %r = zext i16 %i to i32 |
| 59 ; CHECK-NEXT: ret i32 %r |
| 60 ; CHECK-NEXT: } |
| 61 |
| 62 define i32 @test_atomic_load_32(i32 %iptr) { |
| 63 entry: |
| 64 %ptr = inttoptr i32 %iptr to i32* |
| 65 %r = call i32 @llvm.nacl.atomic.load.i32(i32* %ptr, i32 6) |
| 66 ret i32 %r |
| 67 } |
| 68 |
| 69 ; CHECK-NEXT: define i32 @test_atomic_load_32(i32 %iptr) { |
| 70 ; CHECK-NEXT: entry: |
| 71 ; CHECK-NEXT: %r = call i32 @llvm.nacl.atomic.load.i32(i32 %iptr, i32 6) |
| 72 ; CHECK-NEXT: ret i32 %r |
| 73 ; CHECK-NEXT: } |
| 74 |
| 75 define i64 @test_atomic_load_64(i32 %iptr) { |
| 76 entry: |
| 77 %ptr = inttoptr i32 %iptr to i64* |
| 78 %r = call i64 @llvm.nacl.atomic.load.i64(i64* %ptr, i32 6) |
| 79 ret i64 %r |
| 80 } |
| 81 |
| 82 ; CHECK-NEXT: define i64 @test_atomic_load_64(i32 %iptr) { |
| 83 ; CHECK-NEXT: entry: |
| 84 ; CHECK-NEXT: %r = call i64 @llvm.nacl.atomic.load.i64(i32 %iptr, i32 6) |
| 85 ; CHECK-NEXT: ret i64 %r |
| 86 ; CHECK-NEXT: } |
| 87 |
| 88 ;;; Store |
| 89 |
| 90 define void @test_atomic_store_8(i32 %iptr, i32 %v) { |
| 91 entry: |
| 92 %truncv = trunc i32 %v to i8 |
| 93 %ptr = inttoptr i32 %iptr to i8* |
| 94 call void @llvm.nacl.atomic.store.i8(i8 %truncv, i8* %ptr, i32 6) |
| 95 ret void |
| 96 } |
| 97 |
| 98 ; CHECK-NEXT: define void @test_atomic_store_8(i32 %iptr, i32 %v) { |
| 99 ; CHECK-NEXT: entry: |
| 100 ; CHECK-NEXT: %truncv = trunc i32 %v to i8 |
| 101 ; CHECK-NEXT: call void @llvm.nacl.atomic.store.i8(i8 %truncv, i32 %iptr, i32
6) |
| 102 ; CHECK-NEXT: ret void |
| 103 ; CHECK-NEXT: } |
| 104 |
| 105 define void @test_atomic_store_16(i32 %iptr, i32 %v) { |
| 106 entry: |
| 107 %truncv = trunc i32 %v to i16 |
| 108 %ptr = inttoptr i32 %iptr to i16* |
| 109 call void @llvm.nacl.atomic.store.i16(i16 %truncv, i16* %ptr, i32 6) |
| 110 ret void |
| 111 } |
| 112 |
| 113 ; CHECK-NEXT: define void @test_atomic_store_16(i32 %iptr, i32 %v) { |
| 114 ; CHECK-NEXT: entry: |
| 115 ; CHECK-NEXT: %truncv = trunc i32 %v to i16 |
| 116 ; CHECK-NEXT: call void @llvm.nacl.atomic.store.i16(i16 %truncv, i32 %iptr, i3
2 6) |
| 117 ; CHECK-NEXT: ret void |
| 118 ; CHECK-NEXT: } |
| 119 |
| 120 define void @test_atomic_store_32(i32 %iptr, i32 %v) { |
| 121 entry: |
| 122 %ptr = inttoptr i32 %iptr to i32* |
| 123 call void @llvm.nacl.atomic.store.i32(i32 %v, i32* %ptr, i32 6) |
| 124 ret void |
| 125 } |
| 126 |
| 127 ; CHECK-NEXT: define void @test_atomic_store_32(i32 %iptr, i32 %v) { |
| 128 ; CHECK-NEXT: entry: |
| 129 ; CHECK-NEXT: call void @llvm.nacl.atomic.store.i32(i32 %v, i32 %iptr, i32 6) |
| 130 ; CHECK-NEXT: ret void |
| 131 ; CHECK-NEXT: } |
| 132 |
| 133 define void @test_atomic_store_64(i32 %iptr, i64 %v) { |
| 134 entry: |
| 135 %ptr = inttoptr i32 %iptr to i64* |
| 136 call void @llvm.nacl.atomic.store.i64(i64 %v, i64* %ptr, i32 6) |
| 137 ret void |
| 138 } |
| 139 |
| 140 ; CHECK-NEXT: define void @test_atomic_store_64(i32 %iptr, i64 %v) { |
| 141 ; CHECK-NEXT: entry: |
| 142 ; CHECK-NEXT: call void @llvm.nacl.atomic.store.i64(i64 %v, i32 %iptr, i32 6) |
| 143 ; CHECK-NEXT: ret void |
| 144 ; CHECK-NEXT: } |
| 145 |
| 146 define void @test_atomic_store_64_const(i32 %iptr) { |
| 147 entry: |
| 148 %ptr = inttoptr i32 %iptr to i64* |
| 149 call void @llvm.nacl.atomic.store.i64(i64 12345678901234, i64* %ptr, i32 6) |
| 150 ret void |
| 151 } |
| 152 |
| 153 ; CHECK-NEXT: define void @test_atomic_store_64_const(i32 %iptr) { |
| 154 ; CHECK-NEXT: entry: |
| 155 ; CHECK-NEXT: call void @llvm.nacl.atomic.store.i64(i64 12345678901234, i32 %i
ptr, i32 6) |
| 156 ; CHECK-NEXT: ret void |
| 157 ; CHECK-NEXT: } |
| 158 |
| 159 ;;; RMW |
| 160 |
| 161 ;; add |
| 162 |
| 163 define i32 @test_atomic_rmw_add_8(i32 %iptr, i32 %v) { |
| 164 entry: |
| 165 %trunc = trunc i32 %v to i8 |
| 166 %ptr = inttoptr i32 %iptr to i8* |
| 167 ; "1" is an atomic add, and "6" is sequential consistency. |
| 168 %a = call i8 @llvm.nacl.atomic.rmw.i8(i32 1, i8* %ptr, i8 %trunc, i32 6) |
| 169 %a_ext = zext i8 %a to i32 |
| 170 ret i32 %a_ext |
| 171 } |
| 172 |
| 173 ; CHECK-NEXT: define i32 @test_atomic_rmw_add_8(i32 %iptr, i32 %v) { |
| 174 ; CHECK-NEXT: entry: |
| 175 ; CHECK-NEXT: %trunc = trunc i32 %v to i8 |
| 176 ; CHECK-NEXT: %a = call i8 @llvm.nacl.atomic.rmw.i8(i32 1, i32 %iptr, i8 %trun
c, i32 6) |
| 177 ; CHECK-NEXT: %a_ext = zext i8 %a to i32 |
| 178 ; CHECK-NEXT: ret i32 %a_ext |
| 179 ; CHECK-NEXT: } |
| 180 |
| 181 define i32 @test_atomic_rmw_add_16(i32 %iptr, i32 %v) { |
| 182 entry: |
| 183 %trunc = trunc i32 %v to i16 |
| 184 %ptr = inttoptr i32 %iptr to i16* |
| 185 %a = call i16 @llvm.nacl.atomic.rmw.i16(i32 1, i16* %ptr, i16 %trunc, i32 6) |
| 186 %a_ext = zext i16 %a to i32 |
| 187 ret i32 %a_ext |
| 188 } |
| 189 |
| 190 ; CHECK-NEXT: define i32 @test_atomic_rmw_add_16(i32 %iptr, i32 %v) { |
| 191 ; CHECK-NEXT: entry: |
| 192 ; CHECK-NEXT: %trunc = trunc i32 %v to i16 |
| 193 ; CHECK-NEXT: %a = call i16 @llvm.nacl.atomic.rmw.i16(i32 1, i32 %iptr, i16 %t
runc, i32 6) |
| 194 ; CHECK-NEXT: %a_ext = zext i16 %a to i32 |
| 195 ; CHECK-NEXT: ret i32 %a_ext |
| 196 ; CHECK-NEXT: } |
| 197 |
| 198 define i32 @test_atomic_rmw_add_32(i32 %iptr, i32 %v) { |
| 199 entry: |
| 200 %ptr = inttoptr i32 %iptr to i32* |
| 201 %a = call i32 @llvm.nacl.atomic.rmw.i32(i32 1, i32* %ptr, i32 %v, i32 6) |
| 202 ret i32 %a |
| 203 } |
| 204 |
| 205 ; CHECK-NEXT: define i32 @test_atomic_rmw_add_32(i32 %iptr, i32 %v) { |
| 206 ; CHECK-NEXT: entry: |
| 207 ; CHECK-NEXT: %a = call i32 @llvm.nacl.atomic.rmw.i32(i32 1, i32 %iptr, i32 %v
, i32 6) |
| 208 ; CHECK-NEXT: ret i32 %a |
| 209 ; CHECK-NEXT: } |
| 210 |
| 211 define i64 @test_atomic_rmw_add_64(i32 %iptr, i64 %v) { |
| 212 entry: |
| 213 %ptr = inttoptr i32 %iptr to i64* |
| 214 %a = call i64 @llvm.nacl.atomic.rmw.i64(i32 1, i64* %ptr, i64 %v, i32 6) |
| 215 ret i64 %a |
| 216 } |
| 217 |
| 218 ; CHECK-NEXT: define i64 @test_atomic_rmw_add_64(i32 %iptr, i64 %v) { |
| 219 ; CHECK-NEXT: entry: |
| 220 ; CHECK-NEXT: %a = call i64 @llvm.nacl.atomic.rmw.i64(i32 1, i32 %iptr, i64 %v
, i32 6) |
| 221 ; CHECK-NEXT: ret i64 %a |
| 222 ; CHECK-NEXT: } |
| 223 |
| 224 ;; sub |
| 225 |
| 226 define i32 @test_atomic_rmw_sub_8(i32 %iptr, i32 %v) { |
| 227 entry: |
| 228 %trunc = trunc i32 %v to i8 |
| 229 %ptr = inttoptr i32 %iptr to i8* |
| 230 %a = call i8 @llvm.nacl.atomic.rmw.i8(i32 2, i8* %ptr, i8 %trunc, i32 6) |
| 231 %a_ext = zext i8 %a to i32 |
| 232 ret i32 %a_ext |
| 233 } |
| 234 |
| 235 ; CHECK-NEXT: define i32 @test_atomic_rmw_sub_8(i32 %iptr, i32 %v) { |
| 236 ; CHECK-NEXT: entry: |
| 237 ; CHECK-NEXT: %trunc = trunc i32 %v to i8 |
| 238 ; CHECK-NEXT: %a = call i8 @llvm.nacl.atomic.rmw.i8(i32 2, i32 %iptr, i8 %trun
c, i32 6) |
| 239 ; CHECK-NEXT: %a_ext = zext i8 %a to i32 |
| 240 ; CHECK-NEXT: ret i32 %a_ext |
| 241 ; CHECK-NEXT: } |
| 242 |
| 243 define i32 @test_atomic_rmw_sub_16(i32 %iptr, i32 %v) { |
| 244 entry: |
| 245 %trunc = trunc i32 %v to i16 |
| 246 %ptr = inttoptr i32 %iptr to i16* |
| 247 %a = call i16 @llvm.nacl.atomic.rmw.i16(i32 2, i16* %ptr, i16 %trunc, i32 6) |
| 248 %a_ext = zext i16 %a to i32 |
| 249 ret i32 %a_ext |
| 250 } |
| 251 |
| 252 ; CHECK-NEXT: define i32 @test_atomic_rmw_sub_16(i32 %iptr, i32 %v) { |
| 253 ; CHECK-NEXT: entry: |
| 254 ; CHECK-NEXT: %trunc = trunc i32 %v to i16 |
| 255 ; CHECK-NEXT: %a = call i16 @llvm.nacl.atomic.rmw.i16(i32 2, i32 %iptr, i16 %t
runc, i32 6) |
| 256 ; CHECK-NEXT: %a_ext = zext i16 %a to i32 |
| 257 ; CHECK-NEXT: ret i32 %a_ext |
| 258 ; CHECK-NEXT: } |
| 259 |
| 260 define i32 @test_atomic_rmw_sub_32(i32 %iptr, i32 %v) { |
| 261 entry: |
| 262 %ptr = inttoptr i32 %iptr to i32* |
| 263 %a = call i32 @llvm.nacl.atomic.rmw.i32(i32 2, i32* %ptr, i32 %v, i32 6) |
| 264 ret i32 %a |
| 265 } |
| 266 |
| 267 ; CHECK-NEXT: define i32 @test_atomic_rmw_sub_32(i32 %iptr, i32 %v) { |
| 268 ; CHECK-NEXT: entry: |
| 269 ; CHECK-NEXT: %a = call i32 @llvm.nacl.atomic.rmw.i32(i32 2, i32 %iptr, i32 %v
, i32 6) |
| 270 ; CHECK-NEXT: ret i32 %a |
| 271 ; CHECK-NEXT: } |
| 272 |
| 273 define i64 @test_atomic_rmw_sub_64(i32 %iptr, i64 %v) { |
| 274 entry: |
| 275 %ptr = inttoptr i32 %iptr to i64* |
| 276 %a = call i64 @llvm.nacl.atomic.rmw.i64(i32 2, i64* %ptr, i64 %v, i32 6) |
| 277 ret i64 %a |
| 278 } |
| 279 |
| 280 ; CHECK-NEXT: define i64 @test_atomic_rmw_sub_64(i32 %iptr, i64 %v) { |
| 281 ; CHECK-NEXT: entry: |
| 282 ; CHECK-NEXT: %a = call i64 @llvm.nacl.atomic.rmw.i64(i32 2, i32 %iptr, i64 %v
, i32 6) |
| 283 ; CHECK-NEXT: ret i64 %a |
| 284 ; CHECK-NEXT: } |
| 285 |
| 286 ;; or |
| 287 |
| 288 define i32 @test_atomic_rmw_or_8(i32 %iptr, i32 %v) { |
| 289 entry: |
| 290 %trunc = trunc i32 %v to i8 |
| 291 %ptr = inttoptr i32 %iptr to i8* |
| 292 %a = call i8 @llvm.nacl.atomic.rmw.i8(i32 3, i8* %ptr, i8 %trunc, i32 6) |
| 293 %a_ext = zext i8 %a to i32 |
| 294 ret i32 %a_ext |
| 295 } |
| 296 |
| 297 ; CHECK-NEXT: define i32 @test_atomic_rmw_or_8(i32 %iptr, i32 %v) { |
| 298 ; CHECK-NEXT: entry: |
| 299 ; CHECK-NEXT: %trunc = trunc i32 %v to i8 |
| 300 ; CHECK-NEXT: %a = call i8 @llvm.nacl.atomic.rmw.i8(i32 3, i32 %iptr, i8 %trun
c, i32 6) |
| 301 ; CHECK-NEXT: %a_ext = zext i8 %a to i32 |
| 302 ; CHECK-NEXT: ret i32 %a_ext |
| 303 ; CHECK-NEXT: } |
| 304 |
| 305 define i32 @test_atomic_rmw_or_16(i32 %iptr, i32 %v) { |
| 306 entry: |
| 307 %trunc = trunc i32 %v to i16 |
| 308 %ptr = inttoptr i32 %iptr to i16* |
| 309 %a = call i16 @llvm.nacl.atomic.rmw.i16(i32 3, i16* %ptr, i16 %trunc, i32 6) |
| 310 %a_ext = zext i16 %a to i32 |
| 311 ret i32 %a_ext |
| 312 } |
| 313 |
| 314 ; CHECK-NEXT: define i32 @test_atomic_rmw_or_16(i32 %iptr, i32 %v) { |
| 315 ; CHECK-NEXT: entry: |
| 316 ; CHECK-NEXT: %trunc = trunc i32 %v to i16 |
| 317 ; CHECK-NEXT: %a = call i16 @llvm.nacl.atomic.rmw.i16(i32 3, i32 %iptr, i16 %t
runc, i32 6) |
| 318 ; CHECK-NEXT: %a_ext = zext i16 %a to i32 |
| 319 ; CHECK-NEXT: ret i32 %a_ext |
| 320 ; CHECK-NEXT: } |
| 321 |
| 322 define i32 @test_atomic_rmw_or_32(i32 %iptr, i32 %v) { |
| 323 entry: |
| 324 %ptr = inttoptr i32 %iptr to i32* |
| 325 %a = call i32 @llvm.nacl.atomic.rmw.i32(i32 3, i32* %ptr, i32 %v, i32 6) |
| 326 ret i32 %a |
| 327 } |
| 328 |
| 329 ; CHECK-NEXT: define i32 @test_atomic_rmw_or_32(i32 %iptr, i32 %v) { |
| 330 ; CHECK-NEXT: entry: |
| 331 ; CHECK-NEXT: %a = call i32 @llvm.nacl.atomic.rmw.i32(i32 3, i32 %iptr, i32 %v
, i32 6) |
| 332 ; CHECK-NEXT: ret i32 %a |
| 333 ; CHECK-NEXT: } |
| 334 |
| 335 define i64 @test_atomic_rmw_or_64(i32 %iptr, i64 %v) { |
| 336 entry: |
| 337 %ptr = inttoptr i32 %iptr to i64* |
| 338 %a = call i64 @llvm.nacl.atomic.rmw.i64(i32 3, i64* %ptr, i64 %v, i32 6) |
| 339 ret i64 %a |
| 340 } |
| 341 |
| 342 ; CHECK-NEXT: define i64 @test_atomic_rmw_or_64(i32 %iptr, i64 %v) { |
| 343 ; CHECK-NEXT: entry: |
| 344 ; CHECK-NEXT: %a = call i64 @llvm.nacl.atomic.rmw.i64(i32 3, i32 %iptr, i64 %v
, i32 6) |
| 345 ; CHECK-NEXT: ret i64 %a |
| 346 ; CHECK-NEXT: } |
| 347 |
| 348 ;; and |
| 349 |
| 350 define i32 @test_atomic_rmw_and_8(i32 %iptr, i32 %v) { |
| 351 entry: |
| 352 %trunc = trunc i32 %v to i8 |
| 353 %ptr = inttoptr i32 %iptr to i8* |
| 354 %a = call i8 @llvm.nacl.atomic.rmw.i8(i32 4, i8* %ptr, i8 %trunc, i32 6) |
| 355 %a_ext = zext i8 %a to i32 |
| 356 ret i32 %a_ext |
| 357 } |
| 358 |
| 359 ; CHECK-NEXT: define i32 @test_atomic_rmw_and_8(i32 %iptr, i32 %v) { |
| 360 ; CHECK-NEXT: entry: |
| 361 ; CHECK-NEXT: %trunc = trunc i32 %v to i8 |
| 362 ; CHECK-NEXT: %a = call i8 @llvm.nacl.atomic.rmw.i8(i32 4, i32 %iptr, i8 %trun
c, i32 6) |
| 363 ; CHECK-NEXT: %a_ext = zext i8 %a to i32 |
| 364 ; CHECK-NEXT: ret i32 %a_ext |
| 365 ; CHECK-NEXT: } |
| 366 |
| 367 define i32 @test_atomic_rmw_and_16(i32 %iptr, i32 %v) { |
| 368 entry: |
| 369 %trunc = trunc i32 %v to i16 |
| 370 %ptr = inttoptr i32 %iptr to i16* |
| 371 %a = call i16 @llvm.nacl.atomic.rmw.i16(i32 4, i16* %ptr, i16 %trunc, i32 6) |
| 372 %a_ext = zext i16 %a to i32 |
| 373 ret i32 %a_ext |
| 374 } |
| 375 |
| 376 ; CHECK-NEXT: define i32 @test_atomic_rmw_and_16(i32 %iptr, i32 %v) { |
| 377 ; CHECK-NEXT: entry: |
| 378 ; CHECK-NEXT: %trunc = trunc i32 %v to i16 |
| 379 ; CHECK-NEXT: %a = call i16 @llvm.nacl.atomic.rmw.i16(i32 4, i32 %iptr, i16 %t
runc, i32 6) |
| 380 ; CHECK-NEXT: %a_ext = zext i16 %a to i32 |
| 381 ; CHECK-NEXT: ret i32 %a_ext |
| 382 ; CHECK-NEXT: } |
| 383 |
| 384 define i32 @test_atomic_rmw_and_32(i32 %iptr, i32 %v) { |
| 385 entry: |
| 386 %ptr = inttoptr i32 %iptr to i32* |
| 387 %a = call i32 @llvm.nacl.atomic.rmw.i32(i32 4, i32* %ptr, i32 %v, i32 6) |
| 388 ret i32 %a |
| 389 } |
| 390 |
| 391 ; CHECK-NEXT: define i32 @test_atomic_rmw_and_32(i32 %iptr, i32 %v) { |
| 392 ; CHECK-NEXT: entry: |
| 393 ; CHECK-NEXT: %a = call i32 @llvm.nacl.atomic.rmw.i32(i32 4, i32 %iptr, i32 %v
, i32 6) |
| 394 ; CHECK-NEXT: ret i32 %a |
| 395 ; CHECK-NEXT: } |
| 396 |
| 397 define i64 @test_atomic_rmw_and_64(i32 %iptr, i64 %v) { |
| 398 entry: |
| 399 %ptr = inttoptr i32 %iptr to i64* |
| 400 %a = call i64 @llvm.nacl.atomic.rmw.i64(i32 4, i64* %ptr, i64 %v, i32 6) |
| 401 ret i64 %a |
| 402 } |
| 403 |
| 404 ; CHECK-NEXT: define i64 @test_atomic_rmw_and_64(i32 %iptr, i64 %v) { |
| 405 ; CHECK-NEXT: entry: |
| 406 ; CHECK-NEXT: %a = call i64 @llvm.nacl.atomic.rmw.i64(i32 4, i32 %iptr, i64 %v
, i32 6) |
| 407 ; CHECK-NEXT: ret i64 %a |
| 408 ; CHECK-NEXT: } |
| 409 |
| 410 ;; xor |
| 411 |
| 412 define i32 @test_atomic_rmw_xor_8(i32 %iptr, i32 %v) { |
| 413 entry: |
| 414 %trunc = trunc i32 %v to i8 |
| 415 %ptr = inttoptr i32 %iptr to i8* |
| 416 %a = call i8 @llvm.nacl.atomic.rmw.i8(i32 5, i8* %ptr, i8 %trunc, i32 6) |
| 417 %a_ext = zext i8 %a to i32 |
| 418 ret i32 %a_ext |
| 419 } |
| 420 |
| 421 ; CHECK-NEXT: define i32 @test_atomic_rmw_xor_8(i32 %iptr, i32 %v) { |
| 422 ; CHECK-NEXT: entry: |
| 423 ; CHECK-NEXT: %trunc = trunc i32 %v to i8 |
| 424 ; CHECK-NEXT: %a = call i8 @llvm.nacl.atomic.rmw.i8(i32 5, i32 %iptr, i8 %trun
c, i32 6) |
| 425 ; CHECK-NEXT: %a_ext = zext i8 %a to i32 |
| 426 ; CHECK-NEXT: ret i32 %a_ext |
| 427 ; CHECK-NEXT: } |
| 428 |
| 429 define i32 @test_atomic_rmw_xor_16(i32 %iptr, i32 %v) { |
| 430 entry: |
| 431 %trunc = trunc i32 %v to i16 |
| 432 %ptr = inttoptr i32 %iptr to i16* |
| 433 %a = call i16 @llvm.nacl.atomic.rmw.i16(i32 5, i16* %ptr, i16 %trunc, i32 6) |
| 434 %a_ext = zext i16 %a to i32 |
| 435 ret i32 %a_ext |
| 436 } |
| 437 |
| 438 ; CHECK-NEXT: define i32 @test_atomic_rmw_xor_16(i32 %iptr, i32 %v) { |
| 439 ; CHECK-NEXT: entry: |
| 440 ; CHECK-NEXT: %trunc = trunc i32 %v to i16 |
| 441 ; CHECK-NEXT: %a = call i16 @llvm.nacl.atomic.rmw.i16(i32 5, i32 %iptr, i16 %t
runc, i32 6) |
| 442 ; CHECK-NEXT: %a_ext = zext i16 %a to i32 |
| 443 ; CHECK-NEXT: ret i32 %a_ext |
| 444 ; CHECK-NEXT: } |
| 445 |
| 446 define i32 @test_atomic_rmw_xor_32(i32 %iptr, i32 %v) { |
| 447 entry: |
| 448 %ptr = inttoptr i32 %iptr to i32* |
| 449 %a = call i32 @llvm.nacl.atomic.rmw.i32(i32 5, i32* %ptr, i32 %v, i32 6) |
| 450 ret i32 %a |
| 451 } |
| 452 |
| 453 ; CHECK-NEXT: define i32 @test_atomic_rmw_xor_32(i32 %iptr, i32 %v) { |
| 454 ; CHECK-NEXT: entry: |
| 455 ; CHECK-NEXT: %a = call i32 @llvm.nacl.atomic.rmw.i32(i32 5, i32 %iptr, i32 %v
, i32 6) |
| 456 ; CHECK-NEXT: ret i32 %a |
| 457 ; CHECK-NEXT: } |
| 458 |
| 459 define i64 @test_atomic_rmw_xor_64(i32 %iptr, i64 %v) { |
| 460 entry: |
| 461 %ptr = inttoptr i32 %iptr to i64* |
| 462 %a = call i64 @llvm.nacl.atomic.rmw.i64(i32 5, i64* %ptr, i64 %v, i32 6) |
| 463 ret i64 %a |
| 464 } |
| 465 |
| 466 ; CHECK-NEXT: define i64 @test_atomic_rmw_xor_64(i32 %iptr, i64 %v) { |
| 467 ; CHECK-NEXT: entry: |
| 468 ; CHECK-NEXT: %a = call i64 @llvm.nacl.atomic.rmw.i64(i32 5, i32 %iptr, i64 %v
, i32 6) |
| 469 ; CHECK-NEXT: ret i64 %a |
| 470 ; CHECK-NEXT: } |
| 471 |
| 472 ;; exchange |
| 473 |
| 474 define i32 @test_atomic_rmw_xchg_8(i32 %iptr, i32 %v) { |
| 475 entry: |
| 476 %trunc = trunc i32 %v to i8 |
| 477 %ptr = inttoptr i32 %iptr to i8* |
| 478 %a = call i8 @llvm.nacl.atomic.rmw.i8(i32 6, i8* %ptr, i8 %trunc, i32 6) |
| 479 %a_ext = zext i8 %a to i32 |
| 480 ret i32 %a_ext |
| 481 } |
| 482 |
| 483 ; CHECK-NEXT: define i32 @test_atomic_rmw_xchg_8(i32 %iptr, i32 %v) { |
| 484 ; CHECK-NEXT: entry: |
| 485 ; CHECK-NEXT: %trunc = trunc i32 %v to i8 |
| 486 ; CHECK-NEXT: %a = call i8 @llvm.nacl.atomic.rmw.i8(i32 6, i32 %iptr, i8 %trun
c, i32 6) |
| 487 ; CHECK-NEXT: %a_ext = zext i8 %a to i32 |
| 488 ; CHECK-NEXT: ret i32 %a_ext |
| 489 ; CHECK-NEXT: } |
| 490 |
| 491 define i32 @test_atomic_rmw_xchg_16(i32 %iptr, i32 %v) { |
| 492 entry: |
| 493 %trunc = trunc i32 %v to i16 |
| 494 %ptr = inttoptr i32 %iptr to i16* |
| 495 %a = call i16 @llvm.nacl.atomic.rmw.i16(i32 6, i16* %ptr, i16 %trunc, i32 6) |
| 496 %a_ext = zext i16 %a to i32 |
| 497 ret i32 %a_ext |
| 498 } |
| 499 |
| 500 ; CHECK-NEXT: define i32 @test_atomic_rmw_xchg_16(i32 %iptr, i32 %v) { |
| 501 ; CHECK-NEXT: entry: |
| 502 ; CHECK-NEXT: %trunc = trunc i32 %v to i16 |
| 503 ; CHECK-NEXT: %a = call i16 @llvm.nacl.atomic.rmw.i16(i32 6, i32 %iptr, i16 %t
runc, i32 6) |
| 504 ; CHECK-NEXT: %a_ext = zext i16 %a to i32 |
| 505 ; CHECK-NEXT: ret i32 %a_ext |
| 506 ; CHECK-NEXT: } |
| 507 |
| 508 define i32 @test_atomic_rmw_xchg_32(i32 %iptr, i32 %v) { |
| 509 entry: |
| 510 %ptr = inttoptr i32 %iptr to i32* |
| 511 %a = call i32 @llvm.nacl.atomic.rmw.i32(i32 6, i32* %ptr, i32 %v, i32 6) |
| 512 ret i32 %a |
| 513 } |
| 514 |
| 515 ; CHECK-NEXT: define i32 @test_atomic_rmw_xchg_32(i32 %iptr, i32 %v) { |
| 516 ; CHECK-NEXT: entry: |
| 517 ; CHECK-NEXT: %a = call i32 @llvm.nacl.atomic.rmw.i32(i32 6, i32 %iptr, i32 %v
, i32 6) |
| 518 ; CHECK-NEXT: ret i32 %a |
| 519 ; CHECK-NEXT: } |
| 520 |
| 521 define i64 @test_atomic_rmw_xchg_64(i32 %iptr, i64 %v) { |
| 522 entry: |
| 523 %ptr = inttoptr i32 %iptr to i64* |
| 524 %a = call i64 @llvm.nacl.atomic.rmw.i64(i32 6, i64* %ptr, i64 %v, i32 6) |
| 525 ret i64 %a |
| 526 } |
| 527 |
| 528 ; CHECK-NEXT: define i64 @test_atomic_rmw_xchg_64(i32 %iptr, i64 %v) { |
| 529 ; CHECK-NEXT: entry: |
| 530 ; CHECK-NEXT: %a = call i64 @llvm.nacl.atomic.rmw.i64(i32 6, i32 %iptr, i64 %v
, i32 6) |
| 531 ; CHECK-NEXT: ret i64 %a |
| 532 ; CHECK-NEXT: } |
| 533 |
| 534 ;;;; Cmpxchg |
| 535 |
| 536 define i32 @test_atomic_cmpxchg_8(i32 %iptr, i32 %expected, i32 %desired) { |
| 537 entry: |
| 538 %trunc_exp = trunc i32 %expected to i8 |
| 539 %trunc_des = trunc i32 %desired to i8 |
| 540 %ptr = inttoptr i32 %iptr to i8* |
| 541 %old = call i8 @llvm.nacl.atomic.cmpxchg.i8(i8* %ptr, i8 %trunc_exp, |
| 542 i8 %trunc_des, i32 6, i32 6) |
| 543 %old_ext = zext i8 %old to i32 |
| 544 ret i32 %old_ext |
| 545 } |
| 546 |
| 547 ; CHECK-NEXT: define i32 @test_atomic_cmpxchg_8(i32 %iptr, i32 %expected, i32 %d
esired) { |
| 548 ; CHECK-NEXT: entry: |
| 549 ; CHECK-NEXT: %trunc_exp = trunc i32 %expected to i8 |
| 550 ; CHECK-NEXT: %trunc_des = trunc i32 %desired to i8 |
| 551 ; CHECK-NEXT: %old = call i8 @llvm.nacl.atomic.cmpxchg.i8(i32 %iptr, i8 %trunc
_exp, i8 %trunc_des, i32 6, i32 6) |
| 552 ; CHECK-NEXT: %old_ext = zext i8 %old to i32 |
| 553 ; CHECK-NEXT: ret i32 %old_ext |
| 554 ; CHECK-NEXT: } |
| 555 |
| 556 define i32 @test_atomic_cmpxchg_16(i32 %iptr, i32 %expected, i32 %desired) { |
| 557 entry: |
| 558 %trunc_exp = trunc i32 %expected to i16 |
| 559 %trunc_des = trunc i32 %desired to i16 |
| 560 %ptr = inttoptr i32 %iptr to i16* |
| 561 %old = call i16 @llvm.nacl.atomic.cmpxchg.i16(i16* %ptr, i16 %trunc_exp, |
| 562 i16 %trunc_des, i32 6, i32 6) |
| 563 %old_ext = zext i16 %old to i32 |
| 564 ret i32 %old_ext |
| 565 } |
| 566 |
| 567 ; CHECK-NEXT: define i32 @test_atomic_cmpxchg_16(i32 %iptr, i32 %expected, i32 %
desired) { |
| 568 ; CHECK-NEXT: entry: |
| 569 ; CHECK-NEXT: %trunc_exp = trunc i32 %expected to i16 |
| 570 ; CHECK-NEXT: %trunc_des = trunc i32 %desired to i16 |
| 571 ; CHECK-NEXT: %old = call i16 @llvm.nacl.atomic.cmpxchg.i16(i32 %iptr, i16 %tr
unc_exp, i16 %trunc_des, i32 6, i32 6) |
| 572 ; CHECK-NEXT: %old_ext = zext i16 %old to i32 |
| 573 ; CHECK-NEXT: ret i32 %old_ext |
| 574 ; CHECK-NEXT: } |
| 575 |
| 576 define i32 @test_atomic_cmpxchg_32(i32 %iptr, i32 %expected, i32 %desired) { |
| 577 entry: |
| 578 %ptr = inttoptr i32 %iptr to i32* |
| 579 %old = call i32 @llvm.nacl.atomic.cmpxchg.i32(i32* %ptr, i32 %expected, |
| 580 i32 %desired, i32 6, i32 6) |
| 581 ret i32 %old |
| 582 } |
| 583 |
| 584 ; CHECK-NEXT: define i32 @test_atomic_cmpxchg_32(i32 %iptr, i32 %expected, i32 %
desired) { |
| 585 ; CHECK-NEXT: entry: |
| 586 ; CHECK-NEXT: %old = call i32 @llvm.nacl.atomic.cmpxchg.i32(i32 %iptr, i32 %ex
pected, i32 %desired, i32 6, i32 6) |
| 587 ; CHECK-NEXT: ret i32 %old |
| 588 ; CHECK-NEXT: } |
| 589 |
| 590 define i64 @test_atomic_cmpxchg_64(i32 %iptr, i64 %expected, i64 %desired) { |
| 591 entry: |
| 592 %ptr = inttoptr i32 %iptr to i64* |
| 593 %old = call i64 @llvm.nacl.atomic.cmpxchg.i64(i64* %ptr, i64 %expected, |
| 594 i64 %desired, i32 6, i32 6) |
| 595 ret i64 %old |
| 596 } |
| 597 |
| 598 ; CHECK-NEXT: define i64 @test_atomic_cmpxchg_64(i32 %iptr, i64 %expected, i64 %
desired) { |
| 599 ; CHECK-NEXT: entry: |
| 600 ; CHECK-NEXT: %old = call i64 @llvm.nacl.atomic.cmpxchg.i64(i32 %iptr, i64 %ex
pected, i64 %desired, i32 6, i32 6) |
| 601 ; CHECK-NEXT: ret i64 %old |
| 602 ; CHECK-NEXT: } |
| 603 |
| 604 ;;;; Fence and is-lock-free. |
| 605 |
| 606 define void @test_atomic_fence() { |
| 607 entry: |
| 608 call void @llvm.nacl.atomic.fence(i32 6) |
| 609 ret void |
| 610 } |
| 611 |
| 612 ; CHECK-NEXT: define void @test_atomic_fence() { |
| 613 ; CHECK-NEXT: entry: |
| 614 ; CHECK-NEXT: call void @llvm.nacl.atomic.fence(i32 6) |
| 615 ; CHECK-NEXT: ret void |
| 616 ; CHECK-NEXT: } |
| 617 |
| 618 define void @test_atomic_fence_all() { |
| 619 entry: |
| 620 call void @llvm.nacl.atomic.fence.all() |
| 621 ret void |
| 622 } |
| 623 |
| 624 ; CHECK-NEXT: define void @test_atomic_fence_all() { |
| 625 ; CHECK-NEXT: entry: |
| 626 ; CHECK-NEXT: call void @llvm.nacl.atomic.fence.all() |
| 627 ; CHECK-NEXT: ret void |
| 628 ; CHECK-NEXT: } |
| 629 |
| 630 define i32 @test_atomic_is_lock_free(i32 %iptr) { |
| 631 entry: |
| 632 %ptr = inttoptr i32 %iptr to i8* |
| 633 %i = call i1 @llvm.nacl.atomic.is.lock.free(i32 4, i8* %ptr) |
| 634 %r = zext i1 %i to i32 |
| 635 ret i32 %r |
| 636 } |
| 637 |
| 638 ; CHECK-NEXT: define i32 @test_atomic_is_lock_free(i32 %iptr) { |
| 639 ; CHECK-NEXT: entry: |
| 640 ; CHECK-NEXT: %i = call i1 @llvm.nacl.atomic.is.lock.free(i32 4, i32 %iptr) |
| 641 ; CHECK-NEXT: %r = zext i1 %i to i32 |
| 642 ; CHECK-NEXT: ret i32 %r |
| 643 ; CHECK-NEXT: } |
| 644 |
| OLD | NEW |
|---|
Chromium Code Reviews
Issue 577353003:
Add call instructions to Subzero's bitcode reader. (Closed)
Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master