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| 1 // Copyright 2014 the V8 project authors. All rights reserved. |
| 2 // Use of this source code is governed by a BSD-style license that can be |
| 3 // found in the LICENSE file. |
| 4 |
| 5 #include <stdarg.h> |
| 6 #include <stdlib.h> |
| 7 #include <cmath> |
| 8 |
| 9 #include "src/v8.h" |
| 10 |
| 11 #if V8_TARGET_ARCH_PPC |
| 12 |
| 13 #include "src/assembler.h" |
| 14 #include "src/codegen.h" |
| 15 #include "src/disasm.h" |
| 16 #include "src/ppc/constants-ppc.h" |
| 17 #include "src/ppc/frames-ppc.h" |
| 18 #include "src/ppc/simulator-ppc.h" |
| 19 |
| 20 #if defined(USE_SIMULATOR) |
| 21 |
| 22 // Only build the simulator if not compiling for real PPC hardware. |
| 23 namespace v8 { |
| 24 namespace internal { |
| 25 |
| 26 // This macro provides a platform independent use of sscanf. The reason for |
| 27 // SScanF not being implemented in a platform independent way through |
| 28 // ::v8::internal::OS in the same way as SNPrintF is that the |
| 29 // Windows C Run-Time Library does not provide vsscanf. |
| 30 #define SScanF sscanf // NOLINT |
| 31 |
| 32 // The PPCDebugger class is used by the simulator while debugging simulated |
| 33 // PowerPC code. |
| 34 class PPCDebugger { |
| 35 public: |
| 36 explicit PPCDebugger(Simulator* sim) : sim_(sim) {} |
| 37 ~PPCDebugger(); |
| 38 |
| 39 void Stop(Instruction* instr); |
| 40 void Info(Instruction* instr); |
| 41 void Debug(); |
| 42 |
| 43 private: |
| 44 static const Instr kBreakpointInstr = (TWI | 0x1f * B21); |
| 45 static const Instr kNopInstr = (ORI); // ori, 0,0,0 |
| 46 |
| 47 Simulator* sim_; |
| 48 |
| 49 intptr_t GetRegisterValue(int regnum); |
| 50 double GetRegisterPairDoubleValue(int regnum); |
| 51 double GetFPDoubleRegisterValue(int regnum); |
| 52 bool GetValue(const char* desc, intptr_t* value); |
| 53 bool GetFPDoubleValue(const char* desc, double* value); |
| 54 |
| 55 // Set or delete a breakpoint. Returns true if successful. |
| 56 bool SetBreakpoint(Instruction* break_pc); |
| 57 bool DeleteBreakpoint(Instruction* break_pc); |
| 58 |
| 59 // Undo and redo all breakpoints. This is needed to bracket disassembly and |
| 60 // execution to skip past breakpoints when run from the debugger. |
| 61 void UndoBreakpoints(); |
| 62 void RedoBreakpoints(); |
| 63 }; |
| 64 |
| 65 |
| 66 PPCDebugger::~PPCDebugger() {} |
| 67 |
| 68 |
| 69 #ifdef GENERATED_CODE_COVERAGE |
| 70 static FILE* coverage_log = NULL; |
| 71 |
| 72 |
| 73 static void InitializeCoverage() { |
| 74 char* file_name = getenv("V8_GENERATED_CODE_COVERAGE_LOG"); |
| 75 if (file_name != NULL) { |
| 76 coverage_log = fopen(file_name, "aw+"); |
| 77 } |
| 78 } |
| 79 |
| 80 |
| 81 void PPCDebugger::Stop(Instruction* instr) { |
| 82 // Get the stop code. |
| 83 uint32_t code = instr->SvcValue() & kStopCodeMask; |
| 84 // Retrieve the encoded address, which comes just after this stop. |
| 85 char** msg_address = |
| 86 reinterpret_cast<char**>(sim_->get_pc() + Instruction::kInstrSize); |
| 87 char* msg = *msg_address; |
| 88 DCHECK(msg != NULL); |
| 89 |
| 90 // Update this stop description. |
| 91 if (isWatchedStop(code) && !watched_stops_[code].desc) { |
| 92 watched_stops_[code].desc = msg; |
| 93 } |
| 94 |
| 95 if (strlen(msg) > 0) { |
| 96 if (coverage_log != NULL) { |
| 97 fprintf(coverage_log, "%s\n", msg); |
| 98 fflush(coverage_log); |
| 99 } |
| 100 // Overwrite the instruction and address with nops. |
| 101 instr->SetInstructionBits(kNopInstr); |
| 102 reinterpret_cast<Instruction*>(msg_address)->SetInstructionBits(kNopInstr); |
| 103 } |
| 104 sim_->set_pc(sim_->get_pc() + Instruction::kInstrSize + kPointerSize); |
| 105 } |
| 106 |
| 107 #else // ndef GENERATED_CODE_COVERAGE |
| 108 |
| 109 static void InitializeCoverage() {} |
| 110 |
| 111 |
| 112 void PPCDebugger::Stop(Instruction* instr) { |
| 113 // Get the stop code. |
| 114 // use of kStopCodeMask not right on PowerPC |
| 115 uint32_t code = instr->SvcValue() & kStopCodeMask; |
| 116 // Retrieve the encoded address, which comes just after this stop. |
| 117 char* msg = |
| 118 *reinterpret_cast<char**>(sim_->get_pc() + Instruction::kInstrSize); |
| 119 // Update this stop description. |
| 120 if (sim_->isWatchedStop(code) && !sim_->watched_stops_[code].desc) { |
| 121 sim_->watched_stops_[code].desc = msg; |
| 122 } |
| 123 // Print the stop message and code if it is not the default code. |
| 124 if (code != kMaxStopCode) { |
| 125 PrintF("Simulator hit stop %u: %s\n", code, msg); |
| 126 } else { |
| 127 PrintF("Simulator hit %s\n", msg); |
| 128 } |
| 129 sim_->set_pc(sim_->get_pc() + Instruction::kInstrSize + kPointerSize); |
| 130 Debug(); |
| 131 } |
| 132 #endif |
| 133 |
| 134 |
| 135 void PPCDebugger::Info(Instruction* instr) { |
| 136 // Retrieve the encoded address immediately following the Info breakpoint. |
| 137 char* msg = |
| 138 *reinterpret_cast<char**>(sim_->get_pc() + Instruction::kInstrSize); |
| 139 PrintF("Simulator info %s\n", msg); |
| 140 sim_->set_pc(sim_->get_pc() + Instruction::kInstrSize + kPointerSize); |
| 141 } |
| 142 |
| 143 |
| 144 intptr_t PPCDebugger::GetRegisterValue(int regnum) { |
| 145 return sim_->get_register(regnum); |
| 146 } |
| 147 |
| 148 |
| 149 double PPCDebugger::GetRegisterPairDoubleValue(int regnum) { |
| 150 return sim_->get_double_from_register_pair(regnum); |
| 151 } |
| 152 |
| 153 |
| 154 double PPCDebugger::GetFPDoubleRegisterValue(int regnum) { |
| 155 return sim_->get_double_from_d_register(regnum); |
| 156 } |
| 157 |
| 158 |
| 159 bool PPCDebugger::GetValue(const char* desc, intptr_t* value) { |
| 160 int regnum = Registers::Number(desc); |
| 161 if (regnum != kNoRegister) { |
| 162 *value = GetRegisterValue(regnum); |
| 163 return true; |
| 164 } else { |
| 165 if (strncmp(desc, "0x", 2) == 0) { |
| 166 return SScanF(desc + 2, "%" V8PRIxPTR, |
| 167 reinterpret_cast<uintptr_t*>(value)) == 1; |
| 168 } else { |
| 169 return SScanF(desc, "%" V8PRIuPTR, reinterpret_cast<uintptr_t*>(value)) == |
| 170 1; |
| 171 } |
| 172 } |
| 173 return false; |
| 174 } |
| 175 |
| 176 |
| 177 bool PPCDebugger::GetFPDoubleValue(const char* desc, double* value) { |
| 178 int regnum = FPRegisters::Number(desc); |
| 179 if (regnum != kNoRegister) { |
| 180 *value = sim_->get_double_from_d_register(regnum); |
| 181 return true; |
| 182 } |
| 183 return false; |
| 184 } |
| 185 |
| 186 |
| 187 bool PPCDebugger::SetBreakpoint(Instruction* break_pc) { |
| 188 // Check if a breakpoint can be set. If not return without any side-effects. |
| 189 if (sim_->break_pc_ != NULL) { |
| 190 return false; |
| 191 } |
| 192 |
| 193 // Set the breakpoint. |
| 194 sim_->break_pc_ = break_pc; |
| 195 sim_->break_instr_ = break_pc->InstructionBits(); |
| 196 // Not setting the breakpoint instruction in the code itself. It will be set |
| 197 // when the debugger shell continues. |
| 198 return true; |
| 199 } |
| 200 |
| 201 |
| 202 bool PPCDebugger::DeleteBreakpoint(Instruction* break_pc) { |
| 203 if (sim_->break_pc_ != NULL) { |
| 204 sim_->break_pc_->SetInstructionBits(sim_->break_instr_); |
| 205 } |
| 206 |
| 207 sim_->break_pc_ = NULL; |
| 208 sim_->break_instr_ = 0; |
| 209 return true; |
| 210 } |
| 211 |
| 212 |
| 213 void PPCDebugger::UndoBreakpoints() { |
| 214 if (sim_->break_pc_ != NULL) { |
| 215 sim_->break_pc_->SetInstructionBits(sim_->break_instr_); |
| 216 } |
| 217 } |
| 218 |
| 219 |
| 220 void PPCDebugger::RedoBreakpoints() { |
| 221 if (sim_->break_pc_ != NULL) { |
| 222 sim_->break_pc_->SetInstructionBits(kBreakpointInstr); |
| 223 } |
| 224 } |
| 225 |
| 226 |
| 227 void PPCDebugger::Debug() { |
| 228 intptr_t last_pc = -1; |
| 229 bool done = false; |
| 230 |
| 231 #define COMMAND_SIZE 63 |
| 232 #define ARG_SIZE 255 |
| 233 |
| 234 #define STR(a) #a |
| 235 #define XSTR(a) STR(a) |
| 236 |
| 237 char cmd[COMMAND_SIZE + 1]; |
| 238 char arg1[ARG_SIZE + 1]; |
| 239 char arg2[ARG_SIZE + 1]; |
| 240 char* argv[3] = {cmd, arg1, arg2}; |
| 241 |
| 242 // make sure to have a proper terminating character if reaching the limit |
| 243 cmd[COMMAND_SIZE] = 0; |
| 244 arg1[ARG_SIZE] = 0; |
| 245 arg2[ARG_SIZE] = 0; |
| 246 |
| 247 // Undo all set breakpoints while running in the debugger shell. This will |
| 248 // make them invisible to all commands. |
| 249 UndoBreakpoints(); |
| 250 // Disable tracing while simulating |
| 251 bool trace = ::v8::internal::FLAG_trace_sim; |
| 252 ::v8::internal::FLAG_trace_sim = false; |
| 253 |
| 254 while (!done && !sim_->has_bad_pc()) { |
| 255 if (last_pc != sim_->get_pc()) { |
| 256 disasm::NameConverter converter; |
| 257 disasm::Disassembler dasm(converter); |
| 258 // use a reasonably large buffer |
| 259 v8::internal::EmbeddedVector<char, 256> buffer; |
| 260 dasm.InstructionDecode(buffer, reinterpret_cast<byte*>(sim_->get_pc())); |
| 261 PrintF(" 0x%08" V8PRIxPTR " %s\n", sim_->get_pc(), buffer.start()); |
| 262 last_pc = sim_->get_pc(); |
| 263 } |
| 264 char* line = ReadLine("sim> "); |
| 265 if (line == NULL) { |
| 266 break; |
| 267 } else { |
| 268 char* last_input = sim_->last_debugger_input(); |
| 269 if (strcmp(line, "\n") == 0 && last_input != NULL) { |
| 270 line = last_input; |
| 271 } else { |
| 272 // Ownership is transferred to sim_; |
| 273 sim_->set_last_debugger_input(line); |
| 274 } |
| 275 // Use sscanf to parse the individual parts of the command line. At the |
| 276 // moment no command expects more than two parameters. |
| 277 int argc = SScanF(line, |
| 278 "%" XSTR(COMMAND_SIZE) "s " |
| 279 "%" XSTR(ARG_SIZE) "s " |
| 280 "%" XSTR(ARG_SIZE) "s", |
| 281 cmd, arg1, arg2); |
| 282 if ((strcmp(cmd, "si") == 0) || (strcmp(cmd, "stepi") == 0)) { |
| 283 intptr_t value; |
| 284 |
| 285 // If at a breakpoint, proceed past it. |
| 286 if ((reinterpret_cast<Instruction*>(sim_->get_pc())) |
| 287 ->InstructionBits() == 0x7d821008) { |
| 288 sim_->set_pc(sim_->get_pc() + Instruction::kInstrSize); |
| 289 } else { |
| 290 sim_->ExecuteInstruction( |
| 291 reinterpret_cast<Instruction*>(sim_->get_pc())); |
| 292 } |
| 293 |
| 294 if (argc == 2 && last_pc != sim_->get_pc() && GetValue(arg1, &value)) { |
| 295 for (int i = 1; i < value; i++) { |
| 296 disasm::NameConverter converter; |
| 297 disasm::Disassembler dasm(converter); |
| 298 // use a reasonably large buffer |
| 299 v8::internal::EmbeddedVector<char, 256> buffer; |
| 300 dasm.InstructionDecode(buffer, |
| 301 reinterpret_cast<byte*>(sim_->get_pc())); |
| 302 PrintF(" 0x%08" V8PRIxPTR " %s\n", sim_->get_pc(), |
| 303 buffer.start()); |
| 304 sim_->ExecuteInstruction( |
| 305 reinterpret_cast<Instruction*>(sim_->get_pc())); |
| 306 } |
| 307 } |
| 308 } else if ((strcmp(cmd, "c") == 0) || (strcmp(cmd, "cont") == 0)) { |
| 309 // If at a breakpoint, proceed past it. |
| 310 if ((reinterpret_cast<Instruction*>(sim_->get_pc())) |
| 311 ->InstructionBits() == 0x7d821008) { |
| 312 sim_->set_pc(sim_->get_pc() + Instruction::kInstrSize); |
| 313 } else { |
| 314 // Execute the one instruction we broke at with breakpoints disabled. |
| 315 sim_->ExecuteInstruction( |
| 316 reinterpret_cast<Instruction*>(sim_->get_pc())); |
| 317 } |
| 318 // Leave the debugger shell. |
| 319 done = true; |
| 320 } else if ((strcmp(cmd, "p") == 0) || (strcmp(cmd, "print") == 0)) { |
| 321 if (argc == 2 || (argc == 3 && strcmp(arg2, "fp") == 0)) { |
| 322 intptr_t value; |
| 323 double dvalue; |
| 324 if (strcmp(arg1, "all") == 0) { |
| 325 for (int i = 0; i < kNumRegisters; i++) { |
| 326 value = GetRegisterValue(i); |
| 327 PrintF(" %3s: %08" V8PRIxPTR, Registers::Name(i), value); |
| 328 if ((argc == 3 && strcmp(arg2, "fp") == 0) && i < 8 && |
| 329 (i % 2) == 0) { |
| 330 dvalue = GetRegisterPairDoubleValue(i); |
| 331 PrintF(" (%f)\n", dvalue); |
| 332 } else if (i != 0 && !((i + 1) & 3)) { |
| 333 PrintF("\n"); |
| 334 } |
| 335 } |
| 336 PrintF(" pc: %08" V8PRIxPTR " lr: %08" V8PRIxPTR |
| 337 " " |
| 338 "ctr: %08" V8PRIxPTR " xer: %08x cr: %08x\n", |
| 339 sim_->special_reg_pc_, sim_->special_reg_lr_, |
| 340 sim_->special_reg_ctr_, sim_->special_reg_xer_, |
| 341 sim_->condition_reg_); |
| 342 } else if (strcmp(arg1, "alld") == 0) { |
| 343 for (int i = 0; i < kNumRegisters; i++) { |
| 344 value = GetRegisterValue(i); |
| 345 PrintF(" %3s: %08" V8PRIxPTR " %11" V8PRIdPTR, |
| 346 Registers::Name(i), value, value); |
| 347 if ((argc == 3 && strcmp(arg2, "fp") == 0) && i < 8 && |
| 348 (i % 2) == 0) { |
| 349 dvalue = GetRegisterPairDoubleValue(i); |
| 350 PrintF(" (%f)\n", dvalue); |
| 351 } else if (!((i + 1) % 2)) { |
| 352 PrintF("\n"); |
| 353 } |
| 354 } |
| 355 PrintF(" pc: %08" V8PRIxPTR " lr: %08" V8PRIxPTR |
| 356 " " |
| 357 "ctr: %08" V8PRIxPTR " xer: %08x cr: %08x\n", |
| 358 sim_->special_reg_pc_, sim_->special_reg_lr_, |
| 359 sim_->special_reg_ctr_, sim_->special_reg_xer_, |
| 360 sim_->condition_reg_); |
| 361 } else if (strcmp(arg1, "allf") == 0) { |
| 362 for (int i = 0; i < DoubleRegister::kNumRegisters; i++) { |
| 363 dvalue = GetFPDoubleRegisterValue(i); |
| 364 uint64_t as_words = bit_cast<uint64_t>(dvalue); |
| 365 PrintF("%3s: %f 0x%08x %08x\n", FPRegisters::Name(i), dvalue, |
| 366 static_cast<uint32_t>(as_words >> 32), |
| 367 static_cast<uint32_t>(as_words & 0xffffffff)); |
| 368 } |
| 369 } else if (arg1[0] == 'r' && |
| 370 (arg1[1] >= '0' && arg1[1] <= '9' && |
| 371 (arg1[2] == '\0' || (arg1[2] >= '0' && arg1[2] <= '9' && |
| 372 arg1[3] == '\0')))) { |
| 373 int regnum = strtoul(&arg1[1], 0, 10); |
| 374 if (regnum != kNoRegister) { |
| 375 value = GetRegisterValue(regnum); |
| 376 PrintF("%s: 0x%08" V8PRIxPTR " %" V8PRIdPTR "\n", arg1, value, |
| 377 value); |
| 378 } else { |
| 379 PrintF("%s unrecognized\n", arg1); |
| 380 } |
| 381 } else { |
| 382 if (GetValue(arg1, &value)) { |
| 383 PrintF("%s: 0x%08" V8PRIxPTR " %" V8PRIdPTR "\n", arg1, value, |
| 384 value); |
| 385 } else if (GetFPDoubleValue(arg1, &dvalue)) { |
| 386 uint64_t as_words = bit_cast<uint64_t>(dvalue); |
| 387 PrintF("%s: %f 0x%08x %08x\n", arg1, dvalue, |
| 388 static_cast<uint32_t>(as_words >> 32), |
| 389 static_cast<uint32_t>(as_words & 0xffffffff)); |
| 390 } else { |
| 391 PrintF("%s unrecognized\n", arg1); |
| 392 } |
| 393 } |
| 394 } else { |
| 395 PrintF("print <register>\n"); |
| 396 } |
| 397 } else if ((strcmp(cmd, "po") == 0) || |
| 398 (strcmp(cmd, "printobject") == 0)) { |
| 399 if (argc == 2) { |
| 400 intptr_t value; |
| 401 OFStream os(stdout); |
| 402 if (GetValue(arg1, &value)) { |
| 403 Object* obj = reinterpret_cast<Object*>(value); |
| 404 os << arg1 << ": \n"; |
| 405 #ifdef DEBUG |
| 406 obj->Print(os); |
| 407 os << "\n"; |
| 408 #else |
| 409 os << Brief(obj) << "\n"; |
| 410 #endif |
| 411 } else { |
| 412 os << arg1 << " unrecognized\n"; |
| 413 } |
| 414 } else { |
| 415 PrintF("printobject <value>\n"); |
| 416 } |
| 417 } else if (strcmp(cmd, "setpc") == 0) { |
| 418 intptr_t value; |
| 419 |
| 420 if (!GetValue(arg1, &value)) { |
| 421 PrintF("%s unrecognized\n", arg1); |
| 422 continue; |
| 423 } |
| 424 sim_->set_pc(value); |
| 425 } else if (strcmp(cmd, "stack") == 0 || strcmp(cmd, "mem") == 0) { |
| 426 intptr_t* cur = NULL; |
| 427 intptr_t* end = NULL; |
| 428 int next_arg = 1; |
| 429 |
| 430 if (strcmp(cmd, "stack") == 0) { |
| 431 cur = reinterpret_cast<intptr_t*>(sim_->get_register(Simulator::sp)); |
| 432 } else { // "mem" |
| 433 intptr_t value; |
| 434 if (!GetValue(arg1, &value)) { |
| 435 PrintF("%s unrecognized\n", arg1); |
| 436 continue; |
| 437 } |
| 438 cur = reinterpret_cast<intptr_t*>(value); |
| 439 next_arg++; |
| 440 } |
| 441 |
| 442 intptr_t words; // likely inaccurate variable name for 64bit |
| 443 if (argc == next_arg) { |
| 444 words = 10; |
| 445 } else { |
| 446 if (!GetValue(argv[next_arg], &words)) { |
| 447 words = 10; |
| 448 } |
| 449 } |
| 450 end = cur + words; |
| 451 |
| 452 while (cur < end) { |
| 453 PrintF(" 0x%08" V8PRIxPTR ": 0x%08" V8PRIxPTR " %10" V8PRIdPTR, |
| 454 reinterpret_cast<intptr_t>(cur), *cur, *cur); |
| 455 HeapObject* obj = reinterpret_cast<HeapObject*>(*cur); |
| 456 intptr_t value = *cur; |
| 457 Heap* current_heap = v8::internal::Isolate::Current()->heap(); |
| 458 if (((value & 1) == 0) || current_heap->Contains(obj)) { |
| 459 PrintF(" ("); |
| 460 if ((value & 1) == 0) { |
| 461 PrintF("smi %d", PlatformSmiTagging::SmiToInt(obj)); |
| 462 } else { |
| 463 obj->ShortPrint(); |
| 464 } |
| 465 PrintF(")"); |
| 466 } |
| 467 PrintF("\n"); |
| 468 cur++; |
| 469 } |
| 470 } else if (strcmp(cmd, "disasm") == 0 || strcmp(cmd, "di") == 0) { |
| 471 disasm::NameConverter converter; |
| 472 disasm::Disassembler dasm(converter); |
| 473 // use a reasonably large buffer |
| 474 v8::internal::EmbeddedVector<char, 256> buffer; |
| 475 |
| 476 byte* prev = NULL; |
| 477 byte* cur = NULL; |
| 478 byte* end = NULL; |
| 479 |
| 480 if (argc == 1) { |
| 481 cur = reinterpret_cast<byte*>(sim_->get_pc()); |
| 482 end = cur + (10 * Instruction::kInstrSize); |
| 483 } else if (argc == 2) { |
| 484 int regnum = Registers::Number(arg1); |
| 485 if (regnum != kNoRegister || strncmp(arg1, "0x", 2) == 0) { |
| 486 // The argument is an address or a register name. |
| 487 intptr_t value; |
| 488 if (GetValue(arg1, &value)) { |
| 489 cur = reinterpret_cast<byte*>(value); |
| 490 // Disassemble 10 instructions at <arg1>. |
| 491 end = cur + (10 * Instruction::kInstrSize); |
| 492 } |
| 493 } else { |
| 494 // The argument is the number of instructions. |
| 495 intptr_t value; |
| 496 if (GetValue(arg1, &value)) { |
| 497 cur = reinterpret_cast<byte*>(sim_->get_pc()); |
| 498 // Disassemble <arg1> instructions. |
| 499 end = cur + (value * Instruction::kInstrSize); |
| 500 } |
| 501 } |
| 502 } else { |
| 503 intptr_t value1; |
| 504 intptr_t value2; |
| 505 if (GetValue(arg1, &value1) && GetValue(arg2, &value2)) { |
| 506 cur = reinterpret_cast<byte*>(value1); |
| 507 end = cur + (value2 * Instruction::kInstrSize); |
| 508 } |
| 509 } |
| 510 |
| 511 while (cur < end) { |
| 512 prev = cur; |
| 513 cur += dasm.InstructionDecode(buffer, cur); |
| 514 PrintF(" 0x%08" V8PRIxPTR " %s\n", reinterpret_cast<intptr_t>(prev), |
| 515 buffer.start()); |
| 516 } |
| 517 } else if (strcmp(cmd, "gdb") == 0) { |
| 518 PrintF("relinquishing control to gdb\n"); |
| 519 v8::base::OS::DebugBreak(); |
| 520 PrintF("regaining control from gdb\n"); |
| 521 } else if (strcmp(cmd, "break") == 0) { |
| 522 if (argc == 2) { |
| 523 intptr_t value; |
| 524 if (GetValue(arg1, &value)) { |
| 525 if (!SetBreakpoint(reinterpret_cast<Instruction*>(value))) { |
| 526 PrintF("setting breakpoint failed\n"); |
| 527 } |
| 528 } else { |
| 529 PrintF("%s unrecognized\n", arg1); |
| 530 } |
| 531 } else { |
| 532 PrintF("break <address>\n"); |
| 533 } |
| 534 } else if (strcmp(cmd, "del") == 0) { |
| 535 if (!DeleteBreakpoint(NULL)) { |
| 536 PrintF("deleting breakpoint failed\n"); |
| 537 } |
| 538 } else if (strcmp(cmd, "cr") == 0) { |
| 539 PrintF("Condition reg: %08x\n", sim_->condition_reg_); |
| 540 } else if (strcmp(cmd, "lr") == 0) { |
| 541 PrintF("Link reg: %08" V8PRIxPTR "\n", sim_->special_reg_lr_); |
| 542 } else if (strcmp(cmd, "ctr") == 0) { |
| 543 PrintF("Ctr reg: %08" V8PRIxPTR "\n", sim_->special_reg_ctr_); |
| 544 } else if (strcmp(cmd, "xer") == 0) { |
| 545 PrintF("XER: %08x\n", sim_->special_reg_xer_); |
| 546 } else if (strcmp(cmd, "fpscr") == 0) { |
| 547 PrintF("FPSCR: %08x\n", sim_->fp_condition_reg_); |
| 548 } else if (strcmp(cmd, "stop") == 0) { |
| 549 intptr_t value; |
| 550 intptr_t stop_pc = |
| 551 sim_->get_pc() - (Instruction::kInstrSize + kPointerSize); |
| 552 Instruction* stop_instr = reinterpret_cast<Instruction*>(stop_pc); |
| 553 Instruction* msg_address = |
| 554 reinterpret_cast<Instruction*>(stop_pc + Instruction::kInstrSize); |
| 555 if ((argc == 2) && (strcmp(arg1, "unstop") == 0)) { |
| 556 // Remove the current stop. |
| 557 if (sim_->isStopInstruction(stop_instr)) { |
| 558 stop_instr->SetInstructionBits(kNopInstr); |
| 559 msg_address->SetInstructionBits(kNopInstr); |
| 560 } else { |
| 561 PrintF("Not at debugger stop.\n"); |
| 562 } |
| 563 } else if (argc == 3) { |
| 564 // Print information about all/the specified breakpoint(s). |
| 565 if (strcmp(arg1, "info") == 0) { |
| 566 if (strcmp(arg2, "all") == 0) { |
| 567 PrintF("Stop information:\n"); |
| 568 for (uint32_t i = 0; i < sim_->kNumOfWatchedStops; i++) { |
| 569 sim_->PrintStopInfo(i); |
| 570 } |
| 571 } else if (GetValue(arg2, &value)) { |
| 572 sim_->PrintStopInfo(value); |
| 573 } else { |
| 574 PrintF("Unrecognized argument.\n"); |
| 575 } |
| 576 } else if (strcmp(arg1, "enable") == 0) { |
| 577 // Enable all/the specified breakpoint(s). |
| 578 if (strcmp(arg2, "all") == 0) { |
| 579 for (uint32_t i = 0; i < sim_->kNumOfWatchedStops; i++) { |
| 580 sim_->EnableStop(i); |
| 581 } |
| 582 } else if (GetValue(arg2, &value)) { |
| 583 sim_->EnableStop(value); |
| 584 } else { |
| 585 PrintF("Unrecognized argument.\n"); |
| 586 } |
| 587 } else if (strcmp(arg1, "disable") == 0) { |
| 588 // Disable all/the specified breakpoint(s). |
| 589 if (strcmp(arg2, "all") == 0) { |
| 590 for (uint32_t i = 0; i < sim_->kNumOfWatchedStops; i++) { |
| 591 sim_->DisableStop(i); |
| 592 } |
| 593 } else if (GetValue(arg2, &value)) { |
| 594 sim_->DisableStop(value); |
| 595 } else { |
| 596 PrintF("Unrecognized argument.\n"); |
| 597 } |
| 598 } |
| 599 } else { |
| 600 PrintF("Wrong usage. Use help command for more information.\n"); |
| 601 } |
| 602 } else if ((strcmp(cmd, "t") == 0) || strcmp(cmd, "trace") == 0) { |
| 603 ::v8::internal::FLAG_trace_sim = !::v8::internal::FLAG_trace_sim; |
| 604 PrintF("Trace of executed instructions is %s\n", |
| 605 ::v8::internal::FLAG_trace_sim ? "on" : "off"); |
| 606 } else if ((strcmp(cmd, "h") == 0) || (strcmp(cmd, "help") == 0)) { |
| 607 PrintF("cont\n"); |
| 608 PrintF(" continue execution (alias 'c')\n"); |
| 609 PrintF("stepi [num instructions]\n"); |
| 610 PrintF(" step one/num instruction(s) (alias 'si')\n"); |
| 611 PrintF("print <register>\n"); |
| 612 PrintF(" print register content (alias 'p')\n"); |
| 613 PrintF(" use register name 'all' to display all integer registers\n"); |
| 614 PrintF( |
| 615 " use register name 'alld' to display integer registers " |
| 616 "with decimal values\n"); |
| 617 PrintF(" use register name 'rN' to display register number 'N'\n"); |
| 618 PrintF(" add argument 'fp' to print register pair double values\n"); |
| 619 PrintF( |
| 620 " use register name 'allf' to display floating-point " |
| 621 "registers\n"); |
| 622 PrintF("printobject <register>\n"); |
| 623 PrintF(" print an object from a register (alias 'po')\n"); |
| 624 PrintF("cr\n"); |
| 625 PrintF(" print condition register\n"); |
| 626 PrintF("lr\n"); |
| 627 PrintF(" print link register\n"); |
| 628 PrintF("ctr\n"); |
| 629 PrintF(" print ctr register\n"); |
| 630 PrintF("xer\n"); |
| 631 PrintF(" print XER\n"); |
| 632 PrintF("fpscr\n"); |
| 633 PrintF(" print FPSCR\n"); |
| 634 PrintF("stack [<num words>]\n"); |
| 635 PrintF(" dump stack content, default dump 10 words)\n"); |
| 636 PrintF("mem <address> [<num words>]\n"); |
| 637 PrintF(" dump memory content, default dump 10 words)\n"); |
| 638 PrintF("disasm [<instructions>]\n"); |
| 639 PrintF("disasm [<address/register>]\n"); |
| 640 PrintF("disasm [[<address/register>] <instructions>]\n"); |
| 641 PrintF(" disassemble code, default is 10 instructions\n"); |
| 642 PrintF(" from pc (alias 'di')\n"); |
| 643 PrintF("gdb\n"); |
| 644 PrintF(" enter gdb\n"); |
| 645 PrintF("break <address>\n"); |
| 646 PrintF(" set a break point on the address\n"); |
| 647 PrintF("del\n"); |
| 648 PrintF(" delete the breakpoint\n"); |
| 649 PrintF("trace (alias 't')\n"); |
| 650 PrintF(" toogle the tracing of all executed statements\n"); |
| 651 PrintF("stop feature:\n"); |
| 652 PrintF(" Description:\n"); |
| 653 PrintF(" Stops are debug instructions inserted by\n"); |
| 654 PrintF(" the Assembler::stop() function.\n"); |
| 655 PrintF(" When hitting a stop, the Simulator will\n"); |
| 656 PrintF(" stop and and give control to the PPCDebugger.\n"); |
| 657 PrintF(" The first %d stop codes are watched:\n", |
| 658 Simulator::kNumOfWatchedStops); |
| 659 PrintF(" - They can be enabled / disabled: the Simulator\n"); |
| 660 PrintF(" will / won't stop when hitting them.\n"); |
| 661 PrintF(" - The Simulator keeps track of how many times they \n"); |
| 662 PrintF(" are met. (See the info command.) Going over a\n"); |
| 663 PrintF(" disabled stop still increases its counter. \n"); |
| 664 PrintF(" Commands:\n"); |
| 665 PrintF(" stop info all/<code> : print infos about number <code>\n"); |
| 666 PrintF(" or all stop(s).\n"); |
| 667 PrintF(" stop enable/disable all/<code> : enables / disables\n"); |
| 668 PrintF(" all or number <code> stop(s)\n"); |
| 669 PrintF(" stop unstop\n"); |
| 670 PrintF(" ignore the stop instruction at the current location\n"); |
| 671 PrintF(" from now on\n"); |
| 672 } else { |
| 673 PrintF("Unknown command: %s\n", cmd); |
| 674 } |
| 675 } |
| 676 } |
| 677 |
| 678 // Add all the breakpoints back to stop execution and enter the debugger |
| 679 // shell when hit. |
| 680 RedoBreakpoints(); |
| 681 // Restore tracing |
| 682 ::v8::internal::FLAG_trace_sim = trace; |
| 683 |
| 684 #undef COMMAND_SIZE |
| 685 #undef ARG_SIZE |
| 686 |
| 687 #undef STR |
| 688 #undef XSTR |
| 689 } |
| 690 |
| 691 |
| 692 static bool ICacheMatch(void* one, void* two) { |
| 693 DCHECK((reinterpret_cast<intptr_t>(one) & CachePage::kPageMask) == 0); |
| 694 DCHECK((reinterpret_cast<intptr_t>(two) & CachePage::kPageMask) == 0); |
| 695 return one == two; |
| 696 } |
| 697 |
| 698 |
| 699 static uint32_t ICacheHash(void* key) { |
| 700 return static_cast<uint32_t>(reinterpret_cast<uintptr_t>(key)) >> 2; |
| 701 } |
| 702 |
| 703 |
| 704 static bool AllOnOnePage(uintptr_t start, int size) { |
| 705 intptr_t start_page = (start & ~CachePage::kPageMask); |
| 706 intptr_t end_page = ((start + size) & ~CachePage::kPageMask); |
| 707 return start_page == end_page; |
| 708 } |
| 709 |
| 710 |
| 711 void Simulator::set_last_debugger_input(char* input) { |
| 712 DeleteArray(last_debugger_input_); |
| 713 last_debugger_input_ = input; |
| 714 } |
| 715 |
| 716 |
| 717 void Simulator::FlushICache(v8::internal::HashMap* i_cache, void* start_addr, |
| 718 size_t size) { |
| 719 intptr_t start = reinterpret_cast<intptr_t>(start_addr); |
| 720 int intra_line = (start & CachePage::kLineMask); |
| 721 start -= intra_line; |
| 722 size += intra_line; |
| 723 size = ((size - 1) | CachePage::kLineMask) + 1; |
| 724 int offset = (start & CachePage::kPageMask); |
| 725 while (!AllOnOnePage(start, size - 1)) { |
| 726 int bytes_to_flush = CachePage::kPageSize - offset; |
| 727 FlushOnePage(i_cache, start, bytes_to_flush); |
| 728 start += bytes_to_flush; |
| 729 size -= bytes_to_flush; |
| 730 DCHECK_EQ(0, static_cast<int>(start & CachePage::kPageMask)); |
| 731 offset = 0; |
| 732 } |
| 733 if (size != 0) { |
| 734 FlushOnePage(i_cache, start, size); |
| 735 } |
| 736 } |
| 737 |
| 738 |
| 739 CachePage* Simulator::GetCachePage(v8::internal::HashMap* i_cache, void* page) { |
| 740 v8::internal::HashMap::Entry* entry = |
| 741 i_cache->Lookup(page, ICacheHash(page), true); |
| 742 if (entry->value == NULL) { |
| 743 CachePage* new_page = new CachePage(); |
| 744 entry->value = new_page; |
| 745 } |
| 746 return reinterpret_cast<CachePage*>(entry->value); |
| 747 } |
| 748 |
| 749 |
| 750 // Flush from start up to and not including start + size. |
| 751 void Simulator::FlushOnePage(v8::internal::HashMap* i_cache, intptr_t start, |
| 752 int size) { |
| 753 DCHECK(size <= CachePage::kPageSize); |
| 754 DCHECK(AllOnOnePage(start, size - 1)); |
| 755 DCHECK((start & CachePage::kLineMask) == 0); |
| 756 DCHECK((size & CachePage::kLineMask) == 0); |
| 757 void* page = reinterpret_cast<void*>(start & (~CachePage::kPageMask)); |
| 758 int offset = (start & CachePage::kPageMask); |
| 759 CachePage* cache_page = GetCachePage(i_cache, page); |
| 760 char* valid_bytemap = cache_page->ValidityByte(offset); |
| 761 memset(valid_bytemap, CachePage::LINE_INVALID, size >> CachePage::kLineShift); |
| 762 } |
| 763 |
| 764 |
| 765 void Simulator::CheckICache(v8::internal::HashMap* i_cache, |
| 766 Instruction* instr) { |
| 767 intptr_t address = reinterpret_cast<intptr_t>(instr); |
| 768 void* page = reinterpret_cast<void*>(address & (~CachePage::kPageMask)); |
| 769 void* line = reinterpret_cast<void*>(address & (~CachePage::kLineMask)); |
| 770 int offset = (address & CachePage::kPageMask); |
| 771 CachePage* cache_page = GetCachePage(i_cache, page); |
| 772 char* cache_valid_byte = cache_page->ValidityByte(offset); |
| 773 bool cache_hit = (*cache_valid_byte == CachePage::LINE_VALID); |
| 774 char* cached_line = cache_page->CachedData(offset & ~CachePage::kLineMask); |
| 775 if (cache_hit) { |
| 776 // Check that the data in memory matches the contents of the I-cache. |
| 777 CHECK_EQ(0, |
| 778 memcmp(reinterpret_cast<void*>(instr), |
| 779 cache_page->CachedData(offset), Instruction::kInstrSize)); |
| 780 } else { |
| 781 // Cache miss. Load memory into the cache. |
| 782 memcpy(cached_line, line, CachePage::kLineLength); |
| 783 *cache_valid_byte = CachePage::LINE_VALID; |
| 784 } |
| 785 } |
| 786 |
| 787 |
| 788 void Simulator::Initialize(Isolate* isolate) { |
| 789 if (isolate->simulator_initialized()) return; |
| 790 isolate->set_simulator_initialized(true); |
| 791 ::v8::internal::ExternalReference::set_redirector(isolate, |
| 792 &RedirectExternalReference); |
| 793 } |
| 794 |
| 795 |
| 796 Simulator::Simulator(Isolate* isolate) : isolate_(isolate) { |
| 797 i_cache_ = isolate_->simulator_i_cache(); |
| 798 if (i_cache_ == NULL) { |
| 799 i_cache_ = new v8::internal::HashMap(&ICacheMatch); |
| 800 isolate_->set_simulator_i_cache(i_cache_); |
| 801 } |
| 802 Initialize(isolate); |
| 803 // Set up simulator support first. Some of this information is needed to |
| 804 // setup the architecture state. |
| 805 #if V8_TARGET_ARCH_PPC64 |
| 806 size_t stack_size = 2 * 1024 * 1024; // allocate 2MB for stack |
| 807 #else |
| 808 size_t stack_size = 1 * 1024 * 1024; // allocate 1MB for stack |
| 809 #endif |
| 810 stack_ = reinterpret_cast<char*>(malloc(stack_size)); |
| 811 pc_modified_ = false; |
| 812 icount_ = 0; |
| 813 break_pc_ = NULL; |
| 814 break_instr_ = 0; |
| 815 |
| 816 // Set up architecture state. |
| 817 // All registers are initialized to zero to start with. |
| 818 for (int i = 0; i < kNumGPRs; i++) { |
| 819 registers_[i] = 0; |
| 820 } |
| 821 condition_reg_ = 0; |
| 822 fp_condition_reg_ = 0; |
| 823 special_reg_pc_ = 0; |
| 824 special_reg_lr_ = 0; |
| 825 special_reg_ctr_ = 0; |
| 826 |
| 827 // Initializing FP registers. |
| 828 for (int i = 0; i < kNumFPRs; i++) { |
| 829 fp_registers_[i] = 0.0; |
| 830 } |
| 831 |
| 832 // The sp is initialized to point to the bottom (high address) of the |
| 833 // allocated stack area. To be safe in potential stack underflows we leave |
| 834 // some buffer below. |
| 835 registers_[sp] = reinterpret_cast<intptr_t>(stack_) + stack_size - 64; |
| 836 InitializeCoverage(); |
| 837 |
| 838 last_debugger_input_ = NULL; |
| 839 } |
| 840 |
| 841 |
| 842 Simulator::~Simulator() {} |
| 843 |
| 844 |
| 845 // When the generated code calls an external reference we need to catch that in |
| 846 // the simulator. The external reference will be a function compiled for the |
| 847 // host architecture. We need to call that function instead of trying to |
| 848 // execute it with the simulator. We do that by redirecting the external |
| 849 // reference to a svc (Supervisor Call) instruction that is handled by |
| 850 // the simulator. We write the original destination of the jump just at a known |
| 851 // offset from the svc instruction so the simulator knows what to call. |
| 852 class Redirection { |
| 853 public: |
| 854 Redirection(void* external_function, ExternalReference::Type type) |
| 855 : external_function_(external_function), |
| 856 swi_instruction_(rtCallRedirInstr | kCallRtRedirected), |
| 857 type_(type), |
| 858 next_(NULL) { |
| 859 Isolate* isolate = Isolate::Current(); |
| 860 next_ = isolate->simulator_redirection(); |
| 861 Simulator::current(isolate)->FlushICache( |
| 862 isolate->simulator_i_cache(), |
| 863 reinterpret_cast<void*>(&swi_instruction_), Instruction::kInstrSize); |
| 864 isolate->set_simulator_redirection(this); |
| 865 } |
| 866 |
| 867 void* address_of_swi_instruction() { |
| 868 return reinterpret_cast<void*>(&swi_instruction_); |
| 869 } |
| 870 |
| 871 void* external_function() { return external_function_; } |
| 872 ExternalReference::Type type() { return type_; } |
| 873 |
| 874 static Redirection* Get(void* external_function, |
| 875 ExternalReference::Type type) { |
| 876 Isolate* isolate = Isolate::Current(); |
| 877 Redirection* current = isolate->simulator_redirection(); |
| 878 for (; current != NULL; current = current->next_) { |
| 879 if (current->external_function_ == external_function) { |
| 880 DCHECK_EQ(current->type(), type); |
| 881 return current; |
| 882 } |
| 883 } |
| 884 return new Redirection(external_function, type); |
| 885 } |
| 886 |
| 887 static Redirection* FromSwiInstruction(Instruction* swi_instruction) { |
| 888 char* addr_of_swi = reinterpret_cast<char*>(swi_instruction); |
| 889 char* addr_of_redirection = |
| 890 addr_of_swi - OFFSET_OF(Redirection, swi_instruction_); |
| 891 return reinterpret_cast<Redirection*>(addr_of_redirection); |
| 892 } |
| 893 |
| 894 static void* ReverseRedirection(intptr_t reg) { |
| 895 Redirection* redirection = FromSwiInstruction( |
| 896 reinterpret_cast<Instruction*>(reinterpret_cast<void*>(reg))); |
| 897 return redirection->external_function(); |
| 898 } |
| 899 |
| 900 private: |
| 901 void* external_function_; |
| 902 uint32_t swi_instruction_; |
| 903 ExternalReference::Type type_; |
| 904 Redirection* next_; |
| 905 }; |
| 906 |
| 907 |
| 908 void* Simulator::RedirectExternalReference(void* external_function, |
| 909 ExternalReference::Type type) { |
| 910 Redirection* redirection = Redirection::Get(external_function, type); |
| 911 return redirection->address_of_swi_instruction(); |
| 912 } |
| 913 |
| 914 |
| 915 // Get the active Simulator for the current thread. |
| 916 Simulator* Simulator::current(Isolate* isolate) { |
| 917 v8::internal::Isolate::PerIsolateThreadData* isolate_data = |
| 918 isolate->FindOrAllocatePerThreadDataForThisThread(); |
| 919 DCHECK(isolate_data != NULL); |
| 920 |
| 921 Simulator* sim = isolate_data->simulator(); |
| 922 if (sim == NULL) { |
| 923 // TODO(146): delete the simulator object when a thread/isolate goes away. |
| 924 sim = new Simulator(isolate); |
| 925 isolate_data->set_simulator(sim); |
| 926 } |
| 927 return sim; |
| 928 } |
| 929 |
| 930 |
| 931 // Sets the register in the architecture state. |
| 932 void Simulator::set_register(int reg, intptr_t value) { |
| 933 DCHECK((reg >= 0) && (reg < kNumGPRs)); |
| 934 registers_[reg] = value; |
| 935 } |
| 936 |
| 937 |
| 938 // Get the register from the architecture state. |
| 939 intptr_t Simulator::get_register(int reg) const { |
| 940 DCHECK((reg >= 0) && (reg < kNumGPRs)); |
| 941 // Stupid code added to avoid bug in GCC. |
| 942 // See: http://gcc.gnu.org/bugzilla/show_bug.cgi?id=43949 |
| 943 if (reg >= kNumGPRs) return 0; |
| 944 // End stupid code. |
| 945 return registers_[reg]; |
| 946 } |
| 947 |
| 948 |
| 949 double Simulator::get_double_from_register_pair(int reg) { |
| 950 DCHECK((reg >= 0) && (reg < kNumGPRs) && ((reg % 2) == 0)); |
| 951 |
| 952 double dm_val = 0.0; |
| 953 #if !V8_TARGET_ARCH_PPC64 // doesn't make sense in 64bit mode |
| 954 // Read the bits from the unsigned integer register_[] array |
| 955 // into the double precision floating point value and return it. |
| 956 char buffer[sizeof(fp_registers_[0])]; |
| 957 memcpy(buffer, ®isters_[reg], 2 * sizeof(registers_[0])); |
| 958 memcpy(&dm_val, buffer, 2 * sizeof(registers_[0])); |
| 959 #endif |
| 960 return (dm_val); |
| 961 } |
| 962 |
| 963 |
| 964 // Raw access to the PC register. |
| 965 void Simulator::set_pc(intptr_t value) { |
| 966 pc_modified_ = true; |
| 967 special_reg_pc_ = value; |
| 968 } |
| 969 |
| 970 |
| 971 bool Simulator::has_bad_pc() const { |
| 972 return ((special_reg_pc_ == bad_lr) || (special_reg_pc_ == end_sim_pc)); |
| 973 } |
| 974 |
| 975 |
| 976 // Raw access to the PC register without the special adjustment when reading. |
| 977 intptr_t Simulator::get_pc() const { return special_reg_pc_; } |
| 978 |
| 979 |
| 980 // Runtime FP routines take: |
| 981 // - two double arguments |
| 982 // - one double argument and zero or one integer arguments. |
| 983 // All are consructed here from d1, d2 and r3. |
| 984 void Simulator::GetFpArgs(double* x, double* y, intptr_t* z) { |
| 985 *x = get_double_from_d_register(1); |
| 986 *y = get_double_from_d_register(2); |
| 987 *z = get_register(3); |
| 988 } |
| 989 |
| 990 |
| 991 // The return value is in d1. |
| 992 void Simulator::SetFpResult(const double& result) { fp_registers_[1] = result; } |
| 993 |
| 994 |
| 995 void Simulator::TrashCallerSaveRegisters() { |
| 996 // We don't trash the registers with the return value. |
| 997 #if 0 // A good idea to trash volatile registers, needs to be done |
| 998 registers_[2] = 0x50Bad4U; |
| 999 registers_[3] = 0x50Bad4U; |
| 1000 registers_[12] = 0x50Bad4U; |
| 1001 #endif |
| 1002 } |
| 1003 |
| 1004 |
| 1005 uint32_t Simulator::ReadWU(intptr_t addr, Instruction* instr) { |
| 1006 uint32_t* ptr = reinterpret_cast<uint32_t*>(addr); |
| 1007 return *ptr; |
| 1008 } |
| 1009 |
| 1010 |
| 1011 int32_t Simulator::ReadW(intptr_t addr, Instruction* instr) { |
| 1012 int32_t* ptr = reinterpret_cast<int32_t*>(addr); |
| 1013 return *ptr; |
| 1014 } |
| 1015 |
| 1016 |
| 1017 void Simulator::WriteW(intptr_t addr, uint32_t value, Instruction* instr) { |
| 1018 uint32_t* ptr = reinterpret_cast<uint32_t*>(addr); |
| 1019 *ptr = value; |
| 1020 return; |
| 1021 } |
| 1022 |
| 1023 |
| 1024 void Simulator::WriteW(intptr_t addr, int32_t value, Instruction* instr) { |
| 1025 int32_t* ptr = reinterpret_cast<int32_t*>(addr); |
| 1026 *ptr = value; |
| 1027 return; |
| 1028 } |
| 1029 |
| 1030 |
| 1031 uint16_t Simulator::ReadHU(intptr_t addr, Instruction* instr) { |
| 1032 uint16_t* ptr = reinterpret_cast<uint16_t*>(addr); |
| 1033 return *ptr; |
| 1034 } |
| 1035 |
| 1036 |
| 1037 int16_t Simulator::ReadH(intptr_t addr, Instruction* instr) { |
| 1038 int16_t* ptr = reinterpret_cast<int16_t*>(addr); |
| 1039 return *ptr; |
| 1040 } |
| 1041 |
| 1042 |
| 1043 void Simulator::WriteH(intptr_t addr, uint16_t value, Instruction* instr) { |
| 1044 uint16_t* ptr = reinterpret_cast<uint16_t*>(addr); |
| 1045 *ptr = value; |
| 1046 return; |
| 1047 } |
| 1048 |
| 1049 |
| 1050 void Simulator::WriteH(intptr_t addr, int16_t value, Instruction* instr) { |
| 1051 int16_t* ptr = reinterpret_cast<int16_t*>(addr); |
| 1052 *ptr = value; |
| 1053 return; |
| 1054 } |
| 1055 |
| 1056 |
| 1057 uint8_t Simulator::ReadBU(intptr_t addr) { |
| 1058 uint8_t* ptr = reinterpret_cast<uint8_t*>(addr); |
| 1059 return *ptr; |
| 1060 } |
| 1061 |
| 1062 |
| 1063 int8_t Simulator::ReadB(intptr_t addr) { |
| 1064 int8_t* ptr = reinterpret_cast<int8_t*>(addr); |
| 1065 return *ptr; |
| 1066 } |
| 1067 |
| 1068 |
| 1069 void Simulator::WriteB(intptr_t addr, uint8_t value) { |
| 1070 uint8_t* ptr = reinterpret_cast<uint8_t*>(addr); |
| 1071 *ptr = value; |
| 1072 } |
| 1073 |
| 1074 |
| 1075 void Simulator::WriteB(intptr_t addr, int8_t value) { |
| 1076 int8_t* ptr = reinterpret_cast<int8_t*>(addr); |
| 1077 *ptr = value; |
| 1078 } |
| 1079 |
| 1080 |
| 1081 intptr_t* Simulator::ReadDW(intptr_t addr) { |
| 1082 intptr_t* ptr = reinterpret_cast<intptr_t*>(addr); |
| 1083 return ptr; |
| 1084 } |
| 1085 |
| 1086 |
| 1087 void Simulator::WriteDW(intptr_t addr, int64_t value) { |
| 1088 int64_t* ptr = reinterpret_cast<int64_t*>(addr); |
| 1089 *ptr = value; |
| 1090 return; |
| 1091 } |
| 1092 |
| 1093 |
| 1094 // Returns the limit of the stack area to enable checking for stack overflows. |
| 1095 uintptr_t Simulator::StackLimit() const { |
| 1096 // Leave a safety margin of 1024 bytes to prevent overrunning the stack when |
| 1097 // pushing values. |
| 1098 return reinterpret_cast<uintptr_t>(stack_) + 1024; |
| 1099 } |
| 1100 |
| 1101 |
| 1102 // Unsupported instructions use Format to print an error and stop execution. |
| 1103 void Simulator::Format(Instruction* instr, const char* format) { |
| 1104 PrintF("Simulator found unsupported instruction:\n 0x%08" V8PRIxPTR ": %s\n", |
| 1105 reinterpret_cast<intptr_t>(instr), format); |
| 1106 UNIMPLEMENTED(); |
| 1107 } |
| 1108 |
| 1109 |
| 1110 // Calculate C flag value for additions. |
| 1111 bool Simulator::CarryFrom(int32_t left, int32_t right, int32_t carry) { |
| 1112 uint32_t uleft = static_cast<uint32_t>(left); |
| 1113 uint32_t uright = static_cast<uint32_t>(right); |
| 1114 uint32_t urest = 0xffffffffU - uleft; |
| 1115 |
| 1116 return (uright > urest) || |
| 1117 (carry && (((uright + 1) > urest) || (uright > (urest - 1)))); |
| 1118 } |
| 1119 |
| 1120 |
| 1121 // Calculate C flag value for subtractions. |
| 1122 bool Simulator::BorrowFrom(int32_t left, int32_t right) { |
| 1123 uint32_t uleft = static_cast<uint32_t>(left); |
| 1124 uint32_t uright = static_cast<uint32_t>(right); |
| 1125 |
| 1126 return (uright > uleft); |
| 1127 } |
| 1128 |
| 1129 |
| 1130 // Calculate V flag value for additions and subtractions. |
| 1131 bool Simulator::OverflowFrom(int32_t alu_out, int32_t left, int32_t right, |
| 1132 bool addition) { |
| 1133 bool overflow; |
| 1134 if (addition) { |
| 1135 // operands have the same sign |
| 1136 overflow = ((left >= 0 && right >= 0) || (left < 0 && right < 0)) |
| 1137 // and operands and result have different sign |
| 1138 && |
| 1139 ((left < 0 && alu_out >= 0) || (left >= 0 && alu_out < 0)); |
| 1140 } else { |
| 1141 // operands have different signs |
| 1142 overflow = ((left < 0 && right >= 0) || (left >= 0 && right < 0)) |
| 1143 // and first operand and result have different signs |
| 1144 && |
| 1145 ((left < 0 && alu_out >= 0) || (left >= 0 && alu_out < 0)); |
| 1146 } |
| 1147 return overflow; |
| 1148 } |
| 1149 |
| 1150 |
| 1151 #if !V8_TARGET_ARCH_PPC64 |
| 1152 // Calls into the V8 runtime are based on this very simple interface. |
| 1153 // Note: To be able to return two values from some calls the code in runtime.cc |
| 1154 // uses the ObjectPair which is essentially two 32-bit values stuffed into a |
| 1155 // 64-bit value. With the code below we assume that all runtime calls return |
| 1156 // 64 bits of result. If they don't, the r4 result register contains a bogus |
| 1157 // value, which is fine because it is caller-saved. |
| 1158 typedef int64_t (*SimulatorRuntimeCall)(intptr_t arg0, intptr_t arg1, |
| 1159 intptr_t arg2, intptr_t arg3, |
| 1160 intptr_t arg4, intptr_t arg5); |
| 1161 #else |
| 1162 // For 64-bit, we need to be more explicit. |
| 1163 typedef intptr_t (*SimulatorRuntimeCall)(intptr_t arg0, intptr_t arg1, |
| 1164 intptr_t arg2, intptr_t arg3, |
| 1165 intptr_t arg4, intptr_t arg5); |
| 1166 struct ObjectPair { |
| 1167 intptr_t x; |
| 1168 intptr_t y; |
| 1169 }; |
| 1170 |
| 1171 typedef struct ObjectPair (*SimulatorRuntimeObjectPairCall)( |
| 1172 intptr_t arg0, intptr_t arg1, intptr_t arg2, intptr_t arg3, intptr_t arg4, |
| 1173 intptr_t arg5); |
| 1174 #endif |
| 1175 |
| 1176 // These prototypes handle the four types of FP calls. |
| 1177 typedef int (*SimulatorRuntimeCompareCall)(double darg0, double darg1); |
| 1178 typedef double (*SimulatorRuntimeFPFPCall)(double darg0, double darg1); |
| 1179 typedef double (*SimulatorRuntimeFPCall)(double darg0); |
| 1180 typedef double (*SimulatorRuntimeFPIntCall)(double darg0, intptr_t arg0); |
| 1181 |
| 1182 // This signature supports direct call in to API function native callback |
| 1183 // (refer to InvocationCallback in v8.h). |
| 1184 typedef void (*SimulatorRuntimeDirectApiCall)(intptr_t arg0); |
| 1185 typedef void (*SimulatorRuntimeProfilingApiCall)(intptr_t arg0, void* arg1); |
| 1186 |
| 1187 // This signature supports direct call to accessor getter callback. |
| 1188 typedef void (*SimulatorRuntimeDirectGetterCall)(intptr_t arg0, intptr_t arg1); |
| 1189 typedef void (*SimulatorRuntimeProfilingGetterCall)(intptr_t arg0, |
| 1190 intptr_t arg1, void* arg2); |
| 1191 |
| 1192 // Software interrupt instructions are used by the simulator to call into the |
| 1193 // C-based V8 runtime. |
| 1194 void Simulator::SoftwareInterrupt(Instruction* instr) { |
| 1195 int svc = instr->SvcValue(); |
| 1196 switch (svc) { |
| 1197 case kCallRtRedirected: { |
| 1198 // Check if stack is aligned. Error if not aligned is reported below to |
| 1199 // include information on the function called. |
| 1200 bool stack_aligned = |
| 1201 (get_register(sp) & (::v8::internal::FLAG_sim_stack_alignment - 1)) == |
| 1202 0; |
| 1203 Redirection* redirection = Redirection::FromSwiInstruction(instr); |
| 1204 const int kArgCount = 6; |
| 1205 int arg0_regnum = 3; |
| 1206 #if V8_TARGET_ARCH_PPC64 && !ABI_RETURNS_OBJECT_PAIRS_IN_REGS |
| 1207 intptr_t result_buffer = 0; |
| 1208 if (redirection->type() == ExternalReference::BUILTIN_OBJECTPAIR_CALL) { |
| 1209 result_buffer = get_register(r3); |
| 1210 arg0_regnum++; |
| 1211 } |
| 1212 #endif |
| 1213 intptr_t arg[kArgCount]; |
| 1214 for (int i = 0; i < kArgCount; i++) { |
| 1215 arg[i] = get_register(arg0_regnum + i); |
| 1216 } |
| 1217 bool fp_call = |
| 1218 (redirection->type() == ExternalReference::BUILTIN_FP_FP_CALL) || |
| 1219 (redirection->type() == ExternalReference::BUILTIN_COMPARE_CALL) || |
| 1220 (redirection->type() == ExternalReference::BUILTIN_FP_CALL) || |
| 1221 (redirection->type() == ExternalReference::BUILTIN_FP_INT_CALL); |
| 1222 // This is dodgy but it works because the C entry stubs are never moved. |
| 1223 // See comment in codegen-arm.cc and bug 1242173. |
| 1224 intptr_t saved_lr = special_reg_lr_; |
| 1225 intptr_t external = |
| 1226 reinterpret_cast<intptr_t>(redirection->external_function()); |
| 1227 if (fp_call) { |
| 1228 double dval0, dval1; // one or two double parameters |
| 1229 intptr_t ival; // zero or one integer parameters |
| 1230 int iresult = 0; // integer return value |
| 1231 double dresult = 0; // double return value |
| 1232 GetFpArgs(&dval0, &dval1, &ival); |
| 1233 if (::v8::internal::FLAG_trace_sim || !stack_aligned) { |
| 1234 SimulatorRuntimeCall generic_target = |
| 1235 reinterpret_cast<SimulatorRuntimeCall>(external); |
| 1236 switch (redirection->type()) { |
| 1237 case ExternalReference::BUILTIN_FP_FP_CALL: |
| 1238 case ExternalReference::BUILTIN_COMPARE_CALL: |
| 1239 PrintF("Call to host function at %p with args %f, %f", |
| 1240 FUNCTION_ADDR(generic_target), dval0, dval1); |
| 1241 break; |
| 1242 case ExternalReference::BUILTIN_FP_CALL: |
| 1243 PrintF("Call to host function at %p with arg %f", |
| 1244 FUNCTION_ADDR(generic_target), dval0); |
| 1245 break; |
| 1246 case ExternalReference::BUILTIN_FP_INT_CALL: |
| 1247 PrintF("Call to host function at %p with args %f, %" V8PRIdPTR, |
| 1248 FUNCTION_ADDR(generic_target), dval0, ival); |
| 1249 break; |
| 1250 default: |
| 1251 UNREACHABLE(); |
| 1252 break; |
| 1253 } |
| 1254 if (!stack_aligned) { |
| 1255 PrintF(" with unaligned stack %08" V8PRIxPTR "\n", |
| 1256 get_register(sp)); |
| 1257 } |
| 1258 PrintF("\n"); |
| 1259 } |
| 1260 CHECK(stack_aligned); |
| 1261 switch (redirection->type()) { |
| 1262 case ExternalReference::BUILTIN_COMPARE_CALL: { |
| 1263 SimulatorRuntimeCompareCall target = |
| 1264 reinterpret_cast<SimulatorRuntimeCompareCall>(external); |
| 1265 iresult = target(dval0, dval1); |
| 1266 set_register(r3, iresult); |
| 1267 break; |
| 1268 } |
| 1269 case ExternalReference::BUILTIN_FP_FP_CALL: { |
| 1270 SimulatorRuntimeFPFPCall target = |
| 1271 reinterpret_cast<SimulatorRuntimeFPFPCall>(external); |
| 1272 dresult = target(dval0, dval1); |
| 1273 SetFpResult(dresult); |
| 1274 break; |
| 1275 } |
| 1276 case ExternalReference::BUILTIN_FP_CALL: { |
| 1277 SimulatorRuntimeFPCall target = |
| 1278 reinterpret_cast<SimulatorRuntimeFPCall>(external); |
| 1279 dresult = target(dval0); |
| 1280 SetFpResult(dresult); |
| 1281 break; |
| 1282 } |
| 1283 case ExternalReference::BUILTIN_FP_INT_CALL: { |
| 1284 SimulatorRuntimeFPIntCall target = |
| 1285 reinterpret_cast<SimulatorRuntimeFPIntCall>(external); |
| 1286 dresult = target(dval0, ival); |
| 1287 SetFpResult(dresult); |
| 1288 break; |
| 1289 } |
| 1290 default: |
| 1291 UNREACHABLE(); |
| 1292 break; |
| 1293 } |
| 1294 if (::v8::internal::FLAG_trace_sim || !stack_aligned) { |
| 1295 switch (redirection->type()) { |
| 1296 case ExternalReference::BUILTIN_COMPARE_CALL: |
| 1297 PrintF("Returned %08x\n", iresult); |
| 1298 break; |
| 1299 case ExternalReference::BUILTIN_FP_FP_CALL: |
| 1300 case ExternalReference::BUILTIN_FP_CALL: |
| 1301 case ExternalReference::BUILTIN_FP_INT_CALL: |
| 1302 PrintF("Returned %f\n", dresult); |
| 1303 break; |
| 1304 default: |
| 1305 UNREACHABLE(); |
| 1306 break; |
| 1307 } |
| 1308 } |
| 1309 } else if (redirection->type() == ExternalReference::DIRECT_API_CALL) { |
| 1310 // See callers of MacroAssembler::CallApiFunctionAndReturn for |
| 1311 // explanation of register usage. |
| 1312 if (::v8::internal::FLAG_trace_sim || !stack_aligned) { |
| 1313 PrintF("Call to host function at %p args %08" V8PRIxPTR, |
| 1314 reinterpret_cast<void*>(external), arg[0]); |
| 1315 if (!stack_aligned) { |
| 1316 PrintF(" with unaligned stack %08" V8PRIxPTR "\n", |
| 1317 get_register(sp)); |
| 1318 } |
| 1319 PrintF("\n"); |
| 1320 } |
| 1321 CHECK(stack_aligned); |
| 1322 SimulatorRuntimeDirectApiCall target = |
| 1323 reinterpret_cast<SimulatorRuntimeDirectApiCall>(external); |
| 1324 target(arg[0]); |
| 1325 } else if (redirection->type() == ExternalReference::PROFILING_API_CALL) { |
| 1326 // See callers of MacroAssembler::CallApiFunctionAndReturn for |
| 1327 // explanation of register usage. |
| 1328 if (::v8::internal::FLAG_trace_sim || !stack_aligned) { |
| 1329 PrintF("Call to host function at %p args %08" V8PRIxPTR |
| 1330 " %08" V8PRIxPTR, |
| 1331 reinterpret_cast<void*>(external), arg[0], arg[1]); |
| 1332 if (!stack_aligned) { |
| 1333 PrintF(" with unaligned stack %08" V8PRIxPTR "\n", |
| 1334 get_register(sp)); |
| 1335 } |
| 1336 PrintF("\n"); |
| 1337 } |
| 1338 CHECK(stack_aligned); |
| 1339 SimulatorRuntimeProfilingApiCall target = |
| 1340 reinterpret_cast<SimulatorRuntimeProfilingApiCall>(external); |
| 1341 target(arg[0], Redirection::ReverseRedirection(arg[1])); |
| 1342 } else if (redirection->type() == ExternalReference::DIRECT_GETTER_CALL) { |
| 1343 // See callers of MacroAssembler::CallApiFunctionAndReturn for |
| 1344 // explanation of register usage. |
| 1345 if (::v8::internal::FLAG_trace_sim || !stack_aligned) { |
| 1346 PrintF("Call to host function at %p args %08" V8PRIxPTR |
| 1347 " %08" V8PRIxPTR, |
| 1348 reinterpret_cast<void*>(external), arg[0], arg[1]); |
| 1349 if (!stack_aligned) { |
| 1350 PrintF(" with unaligned stack %08" V8PRIxPTR "\n", |
| 1351 get_register(sp)); |
| 1352 } |
| 1353 PrintF("\n"); |
| 1354 } |
| 1355 CHECK(stack_aligned); |
| 1356 SimulatorRuntimeDirectGetterCall target = |
| 1357 reinterpret_cast<SimulatorRuntimeDirectGetterCall>(external); |
| 1358 #if !ABI_PASSES_HANDLES_IN_REGS |
| 1359 arg[0] = *(reinterpret_cast<intptr_t*>(arg[0])); |
| 1360 #endif |
| 1361 target(arg[0], arg[1]); |
| 1362 } else if (redirection->type() == |
| 1363 ExternalReference::PROFILING_GETTER_CALL) { |
| 1364 if (::v8::internal::FLAG_trace_sim || !stack_aligned) { |
| 1365 PrintF("Call to host function at %p args %08" V8PRIxPTR |
| 1366 " %08" V8PRIxPTR " %08" V8PRIxPTR, |
| 1367 reinterpret_cast<void*>(external), arg[0], arg[1], arg[2]); |
| 1368 if (!stack_aligned) { |
| 1369 PrintF(" with unaligned stack %08" V8PRIxPTR "\n", |
| 1370 get_register(sp)); |
| 1371 } |
| 1372 PrintF("\n"); |
| 1373 } |
| 1374 CHECK(stack_aligned); |
| 1375 SimulatorRuntimeProfilingGetterCall target = |
| 1376 reinterpret_cast<SimulatorRuntimeProfilingGetterCall>(external); |
| 1377 #if !ABI_PASSES_HANDLES_IN_REGS |
| 1378 arg[0] = *(reinterpret_cast<intptr_t*>(arg[0])); |
| 1379 #endif |
| 1380 target(arg[0], arg[1], Redirection::ReverseRedirection(arg[2])); |
| 1381 } else { |
| 1382 // builtin call. |
| 1383 if (::v8::internal::FLAG_trace_sim || !stack_aligned) { |
| 1384 SimulatorRuntimeCall target = |
| 1385 reinterpret_cast<SimulatorRuntimeCall>(external); |
| 1386 PrintF( |
| 1387 "Call to host function at %p,\n" |
| 1388 "\t\t\t\targs %08" V8PRIxPTR ", %08" V8PRIxPTR ", %08" V8PRIxPTR |
| 1389 ", %08" V8PRIxPTR ", %08" V8PRIxPTR ", %08" V8PRIxPTR, |
| 1390 FUNCTION_ADDR(target), arg[0], arg[1], arg[2], arg[3], arg[4], |
| 1391 arg[5]); |
| 1392 if (!stack_aligned) { |
| 1393 PrintF(" with unaligned stack %08" V8PRIxPTR "\n", |
| 1394 get_register(sp)); |
| 1395 } |
| 1396 PrintF("\n"); |
| 1397 } |
| 1398 CHECK(stack_aligned); |
| 1399 #if !V8_TARGET_ARCH_PPC64 |
| 1400 DCHECK(redirection->type() == ExternalReference::BUILTIN_CALL); |
| 1401 SimulatorRuntimeCall target = |
| 1402 reinterpret_cast<SimulatorRuntimeCall>(external); |
| 1403 int64_t result = target(arg[0], arg[1], arg[2], arg[3], arg[4], arg[5]); |
| 1404 int32_t lo_res = static_cast<int32_t>(result); |
| 1405 int32_t hi_res = static_cast<int32_t>(result >> 32); |
| 1406 #if V8_TARGET_BIG_ENDIAN |
| 1407 if (::v8::internal::FLAG_trace_sim) { |
| 1408 PrintF("Returned %08x\n", hi_res); |
| 1409 } |
| 1410 set_register(r3, hi_res); |
| 1411 set_register(r4, lo_res); |
| 1412 #else |
| 1413 if (::v8::internal::FLAG_trace_sim) { |
| 1414 PrintF("Returned %08x\n", lo_res); |
| 1415 } |
| 1416 set_register(r3, lo_res); |
| 1417 set_register(r4, hi_res); |
| 1418 #endif |
| 1419 #else |
| 1420 if (redirection->type() == ExternalReference::BUILTIN_CALL) { |
| 1421 SimulatorRuntimeCall target = |
| 1422 reinterpret_cast<SimulatorRuntimeCall>(external); |
| 1423 intptr_t result = |
| 1424 target(arg[0], arg[1], arg[2], arg[3], arg[4], arg[5]); |
| 1425 if (::v8::internal::FLAG_trace_sim) { |
| 1426 PrintF("Returned %08" V8PRIxPTR "\n", result); |
| 1427 } |
| 1428 set_register(r3, result); |
| 1429 } else { |
| 1430 DCHECK(redirection->type() == |
| 1431 ExternalReference::BUILTIN_OBJECTPAIR_CALL); |
| 1432 SimulatorRuntimeObjectPairCall target = |
| 1433 reinterpret_cast<SimulatorRuntimeObjectPairCall>(external); |
| 1434 struct ObjectPair result = |
| 1435 target(arg[0], arg[1], arg[2], arg[3], arg[4], arg[5]); |
| 1436 if (::v8::internal::FLAG_trace_sim) { |
| 1437 PrintF("Returned %08" V8PRIxPTR ", %08" V8PRIxPTR "\n", result.x, |
| 1438 result.y); |
| 1439 } |
| 1440 #if ABI_RETURNS_OBJECT_PAIRS_IN_REGS |
| 1441 set_register(r3, result.x); |
| 1442 set_register(r4, result.y); |
| 1443 #else |
| 1444 memcpy(reinterpret_cast<void*>(result_buffer), &result, |
| 1445 sizeof(struct ObjectPair)); |
| 1446 #endif |
| 1447 } |
| 1448 #endif |
| 1449 } |
| 1450 set_pc(saved_lr); |
| 1451 break; |
| 1452 } |
| 1453 case kBreakpoint: { |
| 1454 PPCDebugger dbg(this); |
| 1455 dbg.Debug(); |
| 1456 break; |
| 1457 } |
| 1458 case kInfo: { |
| 1459 PPCDebugger dbg(this); |
| 1460 dbg.Info(instr); |
| 1461 break; |
| 1462 } |
| 1463 // stop uses all codes greater than 1 << 23. |
| 1464 default: { |
| 1465 if (svc >= (1 << 23)) { |
| 1466 uint32_t code = svc & kStopCodeMask; |
| 1467 if (isWatchedStop(code)) { |
| 1468 IncreaseStopCounter(code); |
| 1469 } |
| 1470 // Stop if it is enabled, otherwise go on jumping over the stop |
| 1471 // and the message address. |
| 1472 if (isEnabledStop(code)) { |
| 1473 PPCDebugger dbg(this); |
| 1474 dbg.Stop(instr); |
| 1475 } else { |
| 1476 set_pc(get_pc() + Instruction::kInstrSize + kPointerSize); |
| 1477 } |
| 1478 } else { |
| 1479 // This is not a valid svc code. |
| 1480 UNREACHABLE(); |
| 1481 break; |
| 1482 } |
| 1483 } |
| 1484 } |
| 1485 } |
| 1486 |
| 1487 |
| 1488 // Stop helper functions. |
| 1489 bool Simulator::isStopInstruction(Instruction* instr) { |
| 1490 return (instr->Bits(27, 24) == 0xF) && (instr->SvcValue() >= kStopCode); |
| 1491 } |
| 1492 |
| 1493 |
| 1494 bool Simulator::isWatchedStop(uint32_t code) { |
| 1495 DCHECK(code <= kMaxStopCode); |
| 1496 return code < kNumOfWatchedStops; |
| 1497 } |
| 1498 |
| 1499 |
| 1500 bool Simulator::isEnabledStop(uint32_t code) { |
| 1501 DCHECK(code <= kMaxStopCode); |
| 1502 // Unwatched stops are always enabled. |
| 1503 return !isWatchedStop(code) || |
| 1504 !(watched_stops_[code].count & kStopDisabledBit); |
| 1505 } |
| 1506 |
| 1507 |
| 1508 void Simulator::EnableStop(uint32_t code) { |
| 1509 DCHECK(isWatchedStop(code)); |
| 1510 if (!isEnabledStop(code)) { |
| 1511 watched_stops_[code].count &= ~kStopDisabledBit; |
| 1512 } |
| 1513 } |
| 1514 |
| 1515 |
| 1516 void Simulator::DisableStop(uint32_t code) { |
| 1517 DCHECK(isWatchedStop(code)); |
| 1518 if (isEnabledStop(code)) { |
| 1519 watched_stops_[code].count |= kStopDisabledBit; |
| 1520 } |
| 1521 } |
| 1522 |
| 1523 |
| 1524 void Simulator::IncreaseStopCounter(uint32_t code) { |
| 1525 DCHECK(code <= kMaxStopCode); |
| 1526 DCHECK(isWatchedStop(code)); |
| 1527 if ((watched_stops_[code].count & ~(1 << 31)) == 0x7fffffff) { |
| 1528 PrintF( |
| 1529 "Stop counter for code %i has overflowed.\n" |
| 1530 "Enabling this code and reseting the counter to 0.\n", |
| 1531 code); |
| 1532 watched_stops_[code].count = 0; |
| 1533 EnableStop(code); |
| 1534 } else { |
| 1535 watched_stops_[code].count++; |
| 1536 } |
| 1537 } |
| 1538 |
| 1539 |
| 1540 // Print a stop status. |
| 1541 void Simulator::PrintStopInfo(uint32_t code) { |
| 1542 DCHECK(code <= kMaxStopCode); |
| 1543 if (!isWatchedStop(code)) { |
| 1544 PrintF("Stop not watched."); |
| 1545 } else { |
| 1546 const char* state = isEnabledStop(code) ? "Enabled" : "Disabled"; |
| 1547 int32_t count = watched_stops_[code].count & ~kStopDisabledBit; |
| 1548 // Don't print the state of unused breakpoints. |
| 1549 if (count != 0) { |
| 1550 if (watched_stops_[code].desc) { |
| 1551 PrintF("stop %i - 0x%x: \t%s, \tcounter = %i, \t%s\n", code, code, |
| 1552 state, count, watched_stops_[code].desc); |
| 1553 } else { |
| 1554 PrintF("stop %i - 0x%x: \t%s, \tcounter = %i\n", code, code, state, |
| 1555 count); |
| 1556 } |
| 1557 } |
| 1558 } |
| 1559 } |
| 1560 |
| 1561 |
| 1562 void Simulator::SetCR0(intptr_t result, bool setSO) { |
| 1563 int bf = 0; |
| 1564 if (result < 0) { |
| 1565 bf |= 0x80000000; |
| 1566 } |
| 1567 if (result > 0) { |
| 1568 bf |= 0x40000000; |
| 1569 } |
| 1570 if (result == 0) { |
| 1571 bf |= 0x20000000; |
| 1572 } |
| 1573 if (setSO) { |
| 1574 bf |= 0x10000000; |
| 1575 } |
| 1576 condition_reg_ = (condition_reg_ & ~0xF0000000) | bf; |
| 1577 } |
| 1578 |
| 1579 |
| 1580 void Simulator::ExecuteBranchConditional(Instruction* instr) { |
| 1581 int bo = instr->Bits(25, 21) << 21; |
| 1582 int offset = (instr->Bits(15, 2) << 18) >> 16; |
| 1583 int condition_bit = instr->Bits(20, 16); |
| 1584 int condition_mask = 0x80000000 >> condition_bit; |
| 1585 switch (bo) { |
| 1586 case DCBNZF: // Decrement CTR; branch if CTR != 0 and condition false |
| 1587 case DCBEZF: // Decrement CTR; branch if CTR == 0 and condition false |
| 1588 UNIMPLEMENTED(); |
| 1589 case BF: { // Branch if condition false |
| 1590 if (!(condition_reg_ & condition_mask)) { |
| 1591 if (instr->Bit(0) == 1) { // LK flag set |
| 1592 special_reg_lr_ = get_pc() + 4; |
| 1593 } |
| 1594 set_pc(get_pc() + offset); |
| 1595 } |
| 1596 break; |
| 1597 } |
| 1598 case DCBNZT: // Decrement CTR; branch if CTR != 0 and condition true |
| 1599 case DCBEZT: // Decrement CTR; branch if CTR == 0 and condition true |
| 1600 UNIMPLEMENTED(); |
| 1601 case BT: { // Branch if condition true |
| 1602 if (condition_reg_ & condition_mask) { |
| 1603 if (instr->Bit(0) == 1) { // LK flag set |
| 1604 special_reg_lr_ = get_pc() + 4; |
| 1605 } |
| 1606 set_pc(get_pc() + offset); |
| 1607 } |
| 1608 break; |
| 1609 } |
| 1610 case DCBNZ: // Decrement CTR; branch if CTR != 0 |
| 1611 case DCBEZ: // Decrement CTR; branch if CTR == 0 |
| 1612 special_reg_ctr_ -= 1; |
| 1613 if ((special_reg_ctr_ == 0) == (bo == DCBEZ)) { |
| 1614 if (instr->Bit(0) == 1) { // LK flag set |
| 1615 special_reg_lr_ = get_pc() + 4; |
| 1616 } |
| 1617 set_pc(get_pc() + offset); |
| 1618 } |
| 1619 break; |
| 1620 case BA: { // Branch always |
| 1621 if (instr->Bit(0) == 1) { // LK flag set |
| 1622 special_reg_lr_ = get_pc() + 4; |
| 1623 } |
| 1624 set_pc(get_pc() + offset); |
| 1625 break; |
| 1626 } |
| 1627 default: |
| 1628 UNIMPLEMENTED(); // Invalid encoding |
| 1629 } |
| 1630 } |
| 1631 |
| 1632 |
| 1633 // Handle execution based on instruction types. |
| 1634 void Simulator::ExecuteExt1(Instruction* instr) { |
| 1635 switch (instr->Bits(10, 1) << 1) { |
| 1636 case MCRF: |
| 1637 UNIMPLEMENTED(); // Not used by V8. |
| 1638 case BCLRX: { |
| 1639 // need to check BO flag |
| 1640 intptr_t old_pc = get_pc(); |
| 1641 set_pc(special_reg_lr_); |
| 1642 if (instr->Bit(0) == 1) { // LK flag set |
| 1643 special_reg_lr_ = old_pc + 4; |
| 1644 } |
| 1645 break; |
| 1646 } |
| 1647 case BCCTRX: { |
| 1648 // need to check BO flag |
| 1649 intptr_t old_pc = get_pc(); |
| 1650 set_pc(special_reg_ctr_); |
| 1651 if (instr->Bit(0) == 1) { // LK flag set |
| 1652 special_reg_lr_ = old_pc + 4; |
| 1653 } |
| 1654 break; |
| 1655 } |
| 1656 case CRNOR: |
| 1657 case RFI: |
| 1658 case CRANDC: |
| 1659 UNIMPLEMENTED(); |
| 1660 case ISYNC: { |
| 1661 // todo - simulate isync |
| 1662 break; |
| 1663 } |
| 1664 case CRXOR: { |
| 1665 int bt = instr->Bits(25, 21); |
| 1666 int ba = instr->Bits(20, 16); |
| 1667 int bb = instr->Bits(15, 11); |
| 1668 int ba_val = ((0x80000000 >> ba) & condition_reg_) == 0 ? 0 : 1; |
| 1669 int bb_val = ((0x80000000 >> bb) & condition_reg_) == 0 ? 0 : 1; |
| 1670 int bt_val = ba_val ^ bb_val; |
| 1671 bt_val = bt_val << (31 - bt); // shift bit to correct destination |
| 1672 condition_reg_ &= ~(0x80000000 >> bt); |
| 1673 condition_reg_ |= bt_val; |
| 1674 break; |
| 1675 } |
| 1676 case CREQV: { |
| 1677 int bt = instr->Bits(25, 21); |
| 1678 int ba = instr->Bits(20, 16); |
| 1679 int bb = instr->Bits(15, 11); |
| 1680 int ba_val = ((0x80000000 >> ba) & condition_reg_) == 0 ? 0 : 1; |
| 1681 int bb_val = ((0x80000000 >> bb) & condition_reg_) == 0 ? 0 : 1; |
| 1682 int bt_val = 1 - (ba_val ^ bb_val); |
| 1683 bt_val = bt_val << (31 - bt); // shift bit to correct destination |
| 1684 condition_reg_ &= ~(0x80000000 >> bt); |
| 1685 condition_reg_ |= bt_val; |
| 1686 break; |
| 1687 } |
| 1688 case CRNAND: |
| 1689 case CRAND: |
| 1690 case CRORC: |
| 1691 case CROR: |
| 1692 default: { |
| 1693 UNIMPLEMENTED(); // Not used by V8. |
| 1694 } |
| 1695 } |
| 1696 } |
| 1697 |
| 1698 |
| 1699 bool Simulator::ExecuteExt2_10bit(Instruction* instr) { |
| 1700 bool found = true; |
| 1701 |
| 1702 int opcode = instr->Bits(10, 1) << 1; |
| 1703 switch (opcode) { |
| 1704 case SRWX: { |
| 1705 int rs = instr->RSValue(); |
| 1706 int ra = instr->RAValue(); |
| 1707 int rb = instr->RBValue(); |
| 1708 uint32_t rs_val = get_register(rs); |
| 1709 uintptr_t rb_val = get_register(rb); |
| 1710 intptr_t result = rs_val >> (rb_val & 0x3f); |
| 1711 set_register(ra, result); |
| 1712 if (instr->Bit(0)) { // RC bit set |
| 1713 SetCR0(result); |
| 1714 } |
| 1715 break; |
| 1716 } |
| 1717 #if V8_TARGET_ARCH_PPC64 |
| 1718 case SRDX: { |
| 1719 int rs = instr->RSValue(); |
| 1720 int ra = instr->RAValue(); |
| 1721 int rb = instr->RBValue(); |
| 1722 uintptr_t rs_val = get_register(rs); |
| 1723 uintptr_t rb_val = get_register(rb); |
| 1724 intptr_t result = rs_val >> (rb_val & 0x7f); |
| 1725 set_register(ra, result); |
| 1726 if (instr->Bit(0)) { // RC bit set |
| 1727 SetCR0(result); |
| 1728 } |
| 1729 break; |
| 1730 } |
| 1731 #endif |
| 1732 case SRAW: { |
| 1733 int rs = instr->RSValue(); |
| 1734 int ra = instr->RAValue(); |
| 1735 int rb = instr->RBValue(); |
| 1736 int32_t rs_val = get_register(rs); |
| 1737 intptr_t rb_val = get_register(rb); |
| 1738 intptr_t result = rs_val >> (rb_val & 0x3f); |
| 1739 set_register(ra, result); |
| 1740 if (instr->Bit(0)) { // RC bit set |
| 1741 SetCR0(result); |
| 1742 } |
| 1743 break; |
| 1744 } |
| 1745 #if V8_TARGET_ARCH_PPC64 |
| 1746 case SRAD: { |
| 1747 int rs = instr->RSValue(); |
| 1748 int ra = instr->RAValue(); |
| 1749 int rb = instr->RBValue(); |
| 1750 intptr_t rs_val = get_register(rs); |
| 1751 intptr_t rb_val = get_register(rb); |
| 1752 intptr_t result = rs_val >> (rb_val & 0x7f); |
| 1753 set_register(ra, result); |
| 1754 if (instr->Bit(0)) { // RC bit set |
| 1755 SetCR0(result); |
| 1756 } |
| 1757 break; |
| 1758 } |
| 1759 #endif |
| 1760 case SRAWIX: { |
| 1761 int ra = instr->RAValue(); |
| 1762 int rs = instr->RSValue(); |
| 1763 int sh = instr->Bits(15, 11); |
| 1764 int32_t rs_val = get_register(rs); |
| 1765 intptr_t result = rs_val >> sh; |
| 1766 set_register(ra, result); |
| 1767 if (instr->Bit(0)) { // RC bit set |
| 1768 SetCR0(result); |
| 1769 } |
| 1770 break; |
| 1771 } |
| 1772 #if V8_TARGET_ARCH_PPC64 |
| 1773 case EXTSW: { |
| 1774 const int shift = kBitsPerPointer - 32; |
| 1775 int ra = instr->RAValue(); |
| 1776 int rs = instr->RSValue(); |
| 1777 intptr_t rs_val = get_register(rs); |
| 1778 intptr_t ra_val = (rs_val << shift) >> shift; |
| 1779 set_register(ra, ra_val); |
| 1780 if (instr->Bit(0)) { // RC bit set |
| 1781 SetCR0(ra_val); |
| 1782 } |
| 1783 break; |
| 1784 } |
| 1785 #endif |
| 1786 case EXTSH: { |
| 1787 const int shift = kBitsPerPointer - 16; |
| 1788 int ra = instr->RAValue(); |
| 1789 int rs = instr->RSValue(); |
| 1790 intptr_t rs_val = get_register(rs); |
| 1791 intptr_t ra_val = (rs_val << shift) >> shift; |
| 1792 set_register(ra, ra_val); |
| 1793 if (instr->Bit(0)) { // RC bit set |
| 1794 SetCR0(ra_val); |
| 1795 } |
| 1796 break; |
| 1797 } |
| 1798 case EXTSB: { |
| 1799 const int shift = kBitsPerPointer - 8; |
| 1800 int ra = instr->RAValue(); |
| 1801 int rs = instr->RSValue(); |
| 1802 intptr_t rs_val = get_register(rs); |
| 1803 intptr_t ra_val = (rs_val << shift) >> shift; |
| 1804 set_register(ra, ra_val); |
| 1805 if (instr->Bit(0)) { // RC bit set |
| 1806 SetCR0(ra_val); |
| 1807 } |
| 1808 break; |
| 1809 } |
| 1810 case LFSUX: |
| 1811 case LFSX: { |
| 1812 int frt = instr->RTValue(); |
| 1813 int ra = instr->RAValue(); |
| 1814 int rb = instr->RBValue(); |
| 1815 intptr_t ra_val = ra == 0 ? 0 : get_register(ra); |
| 1816 intptr_t rb_val = get_register(rb); |
| 1817 int32_t val = ReadW(ra_val + rb_val, instr); |
| 1818 float* fptr = reinterpret_cast<float*>(&val); |
| 1819 set_d_register_from_double(frt, static_cast<double>(*fptr)); |
| 1820 if (opcode == LFSUX) { |
| 1821 DCHECK(ra != 0); |
| 1822 set_register(ra, ra_val + rb_val); |
| 1823 } |
| 1824 break; |
| 1825 } |
| 1826 case LFDUX: |
| 1827 case LFDX: { |
| 1828 int frt = instr->RTValue(); |
| 1829 int ra = instr->RAValue(); |
| 1830 int rb = instr->RBValue(); |
| 1831 intptr_t ra_val = ra == 0 ? 0 : get_register(ra); |
| 1832 intptr_t rb_val = get_register(rb); |
| 1833 double* dptr = reinterpret_cast<double*>(ReadDW(ra_val + rb_val)); |
| 1834 set_d_register_from_double(frt, *dptr); |
| 1835 if (opcode == LFDUX) { |
| 1836 DCHECK(ra != 0); |
| 1837 set_register(ra, ra_val + rb_val); |
| 1838 } |
| 1839 break; |
| 1840 } |
| 1841 case STFSUX: { |
| 1842 case STFSX: |
| 1843 int frs = instr->RSValue(); |
| 1844 int ra = instr->RAValue(); |
| 1845 int rb = instr->RBValue(); |
| 1846 intptr_t ra_val = ra == 0 ? 0 : get_register(ra); |
| 1847 intptr_t rb_val = get_register(rb); |
| 1848 float frs_val = static_cast<float>(get_double_from_d_register(frs)); |
| 1849 int32_t* p = reinterpret_cast<int32_t*>(&frs_val); |
| 1850 WriteW(ra_val + rb_val, *p, instr); |
| 1851 if (opcode == STFSUX) { |
| 1852 DCHECK(ra != 0); |
| 1853 set_register(ra, ra_val + rb_val); |
| 1854 } |
| 1855 break; |
| 1856 } |
| 1857 case STFDUX: { |
| 1858 case STFDX: |
| 1859 int frs = instr->RSValue(); |
| 1860 int ra = instr->RAValue(); |
| 1861 int rb = instr->RBValue(); |
| 1862 intptr_t ra_val = ra == 0 ? 0 : get_register(ra); |
| 1863 intptr_t rb_val = get_register(rb); |
| 1864 double frs_val = get_double_from_d_register(frs); |
| 1865 int64_t* p = reinterpret_cast<int64_t*>(&frs_val); |
| 1866 WriteDW(ra_val + rb_val, *p); |
| 1867 if (opcode == STFDUX) { |
| 1868 DCHECK(ra != 0); |
| 1869 set_register(ra, ra_val + rb_val); |
| 1870 } |
| 1871 break; |
| 1872 } |
| 1873 case SYNC: { |
| 1874 // todo - simulate sync |
| 1875 break; |
| 1876 } |
| 1877 case ICBI: { |
| 1878 // todo - simulate icbi |
| 1879 break; |
| 1880 } |
| 1881 default: { |
| 1882 found = false; |
| 1883 break; |
| 1884 } |
| 1885 } |
| 1886 |
| 1887 if (found) return found; |
| 1888 |
| 1889 found = true; |
| 1890 opcode = instr->Bits(10, 2) << 2; |
| 1891 switch (opcode) { |
| 1892 case SRADIX: { |
| 1893 int ra = instr->RAValue(); |
| 1894 int rs = instr->RSValue(); |
| 1895 int sh = (instr->Bits(15, 11) | (instr->Bit(1) << 5)); |
| 1896 intptr_t rs_val = get_register(rs); |
| 1897 intptr_t result = rs_val >> sh; |
| 1898 set_register(ra, result); |
| 1899 if (instr->Bit(0)) { // RC bit set |
| 1900 SetCR0(result); |
| 1901 } |
| 1902 break; |
| 1903 } |
| 1904 default: { |
| 1905 found = false; |
| 1906 break; |
| 1907 } |
| 1908 } |
| 1909 |
| 1910 return found; |
| 1911 } |
| 1912 |
| 1913 |
| 1914 bool Simulator::ExecuteExt2_9bit_part1(Instruction* instr) { |
| 1915 bool found = true; |
| 1916 |
| 1917 int opcode = instr->Bits(9, 1) << 1; |
| 1918 switch (opcode) { |
| 1919 case TW: { |
| 1920 // used for call redirection in simulation mode |
| 1921 SoftwareInterrupt(instr); |
| 1922 break; |
| 1923 } |
| 1924 case CMP: { |
| 1925 int ra = instr->RAValue(); |
| 1926 int rb = instr->RBValue(); |
| 1927 int cr = instr->Bits(25, 23); |
| 1928 uint32_t bf = 0; |
| 1929 #if V8_TARGET_ARCH_PPC64 |
| 1930 int L = instr->Bit(21); |
| 1931 if (L) { |
| 1932 #endif |
| 1933 intptr_t ra_val = get_register(ra); |
| 1934 intptr_t rb_val = get_register(rb); |
| 1935 if (ra_val < rb_val) { |
| 1936 bf |= 0x80000000; |
| 1937 } |
| 1938 if (ra_val > rb_val) { |
| 1939 bf |= 0x40000000; |
| 1940 } |
| 1941 if (ra_val == rb_val) { |
| 1942 bf |= 0x20000000; |
| 1943 } |
| 1944 #if V8_TARGET_ARCH_PPC64 |
| 1945 } else { |
| 1946 int32_t ra_val = get_register(ra); |
| 1947 int32_t rb_val = get_register(rb); |
| 1948 if (ra_val < rb_val) { |
| 1949 bf |= 0x80000000; |
| 1950 } |
| 1951 if (ra_val > rb_val) { |
| 1952 bf |= 0x40000000; |
| 1953 } |
| 1954 if (ra_val == rb_val) { |
| 1955 bf |= 0x20000000; |
| 1956 } |
| 1957 } |
| 1958 #endif |
| 1959 uint32_t condition_mask = 0xF0000000U >> (cr * 4); |
| 1960 uint32_t condition = bf >> (cr * 4); |
| 1961 condition_reg_ = (condition_reg_ & ~condition_mask) | condition; |
| 1962 break; |
| 1963 } |
| 1964 case SUBFCX: { |
| 1965 int rt = instr->RTValue(); |
| 1966 int ra = instr->RAValue(); |
| 1967 int rb = instr->RBValue(); |
| 1968 // int oe = instr->Bit(10); |
| 1969 uintptr_t ra_val = get_register(ra); |
| 1970 uintptr_t rb_val = get_register(rb); |
| 1971 uintptr_t alu_out = ~ra_val + rb_val + 1; |
| 1972 set_register(rt, alu_out); |
| 1973 // If the sign of rb and alu_out don't match, carry = 0 |
| 1974 if ((alu_out ^ rb_val) & 0x80000000) { |
| 1975 special_reg_xer_ &= ~0xF0000000; |
| 1976 } else { |
| 1977 special_reg_xer_ = (special_reg_xer_ & ~0xF0000000) | 0x20000000; |
| 1978 } |
| 1979 if (instr->Bit(0)) { // RC bit set |
| 1980 SetCR0(alu_out); |
| 1981 } |
| 1982 // todo - handle OE bit |
| 1983 break; |
| 1984 } |
| 1985 case ADDCX: { |
| 1986 int rt = instr->RTValue(); |
| 1987 int ra = instr->RAValue(); |
| 1988 int rb = instr->RBValue(); |
| 1989 // int oe = instr->Bit(10); |
| 1990 uintptr_t ra_val = get_register(ra); |
| 1991 uintptr_t rb_val = get_register(rb); |
| 1992 uintptr_t alu_out = ra_val + rb_val; |
| 1993 // Check overflow |
| 1994 if (~ra_val < rb_val) { |
| 1995 special_reg_xer_ = (special_reg_xer_ & ~0xF0000000) | 0x20000000; |
| 1996 } else { |
| 1997 special_reg_xer_ &= ~0xF0000000; |
| 1998 } |
| 1999 set_register(rt, alu_out); |
| 2000 if (instr->Bit(0)) { // RC bit set |
| 2001 SetCR0(static_cast<intptr_t>(alu_out)); |
| 2002 } |
| 2003 // todo - handle OE bit |
| 2004 break; |
| 2005 } |
| 2006 case MULHWX: { |
| 2007 int rt = instr->RTValue(); |
| 2008 int ra = instr->RAValue(); |
| 2009 int rb = instr->RBValue(); |
| 2010 int32_t ra_val = (get_register(ra) & 0xFFFFFFFF); |
| 2011 int32_t rb_val = (get_register(rb) & 0xFFFFFFFF); |
| 2012 int64_t alu_out = (int64_t)ra_val * (int64_t)rb_val; |
| 2013 alu_out >>= 32; |
| 2014 set_register(rt, alu_out); |
| 2015 if (instr->Bit(0)) { // RC bit set |
| 2016 SetCR0(static_cast<intptr_t>(alu_out)); |
| 2017 } |
| 2018 // todo - handle OE bit |
| 2019 break; |
| 2020 } |
| 2021 case NEGX: { |
| 2022 int rt = instr->RTValue(); |
| 2023 int ra = instr->RAValue(); |
| 2024 intptr_t ra_val = get_register(ra); |
| 2025 intptr_t alu_out = 1 + ~ra_val; |
| 2026 #if V8_TARGET_ARCH_PPC64 |
| 2027 intptr_t one = 1; // work-around gcc |
| 2028 intptr_t kOverflowVal = (one << 63); |
| 2029 #else |
| 2030 intptr_t kOverflowVal = kMinInt; |
| 2031 #endif |
| 2032 set_register(rt, alu_out); |
| 2033 if (instr->Bit(10)) { // OE bit set |
| 2034 if (ra_val == kOverflowVal) { |
| 2035 special_reg_xer_ |= 0xC0000000; // set SO,OV |
| 2036 } else { |
| 2037 special_reg_xer_ &= ~0x40000000; // clear OV |
| 2038 } |
| 2039 } |
| 2040 if (instr->Bit(0)) { // RC bit set |
| 2041 bool setSO = (special_reg_xer_ & 0x80000000); |
| 2042 SetCR0(alu_out, setSO); |
| 2043 } |
| 2044 break; |
| 2045 } |
| 2046 case SLWX: { |
| 2047 int rs = instr->RSValue(); |
| 2048 int ra = instr->RAValue(); |
| 2049 int rb = instr->RBValue(); |
| 2050 uint32_t rs_val = get_register(rs); |
| 2051 uintptr_t rb_val = get_register(rb); |
| 2052 uint32_t result = rs_val << (rb_val & 0x3f); |
| 2053 set_register(ra, result); |
| 2054 if (instr->Bit(0)) { // RC bit set |
| 2055 SetCR0(result); |
| 2056 } |
| 2057 break; |
| 2058 } |
| 2059 #if V8_TARGET_ARCH_PPC64 |
| 2060 case SLDX: { |
| 2061 int rs = instr->RSValue(); |
| 2062 int ra = instr->RAValue(); |
| 2063 int rb = instr->RBValue(); |
| 2064 uintptr_t rs_val = get_register(rs); |
| 2065 uintptr_t rb_val = get_register(rb); |
| 2066 uintptr_t result = rs_val << (rb_val & 0x7f); |
| 2067 set_register(ra, result); |
| 2068 if (instr->Bit(0)) { // RC bit set |
| 2069 SetCR0(result); |
| 2070 } |
| 2071 break; |
| 2072 } |
| 2073 case MFVSRD: { |
| 2074 DCHECK(!instr->Bit(0)); |
| 2075 int frt = instr->RTValue(); |
| 2076 int ra = instr->RAValue(); |
| 2077 double frt_val = get_double_from_d_register(frt); |
| 2078 int64_t* p = reinterpret_cast<int64_t*>(&frt_val); |
| 2079 set_register(ra, *p); |
| 2080 break; |
| 2081 } |
| 2082 case MFVSRWZ: { |
| 2083 DCHECK(!instr->Bit(0)); |
| 2084 int frt = instr->RTValue(); |
| 2085 int ra = instr->RAValue(); |
| 2086 double frt_val = get_double_from_d_register(frt); |
| 2087 int64_t* p = reinterpret_cast<int64_t*>(&frt_val); |
| 2088 set_register(ra, static_cast<uint32_t>(*p)); |
| 2089 break; |
| 2090 } |
| 2091 case MTVSRD: { |
| 2092 DCHECK(!instr->Bit(0)); |
| 2093 int frt = instr->RTValue(); |
| 2094 int ra = instr->RAValue(); |
| 2095 int64_t ra_val = get_register(ra); |
| 2096 double* p = reinterpret_cast<double*>(&ra_val); |
| 2097 set_d_register_from_double(frt, *p); |
| 2098 break; |
| 2099 } |
| 2100 case MTVSRWA: { |
| 2101 DCHECK(!instr->Bit(0)); |
| 2102 int frt = instr->RTValue(); |
| 2103 int ra = instr->RAValue(); |
| 2104 int64_t ra_val = static_cast<int32_t>(get_register(ra)); |
| 2105 double* p = reinterpret_cast<double*>(&ra_val); |
| 2106 set_d_register_from_double(frt, *p); |
| 2107 break; |
| 2108 } |
| 2109 case MTVSRWZ: { |
| 2110 DCHECK(!instr->Bit(0)); |
| 2111 int frt = instr->RTValue(); |
| 2112 int ra = instr->RAValue(); |
| 2113 uint64_t ra_val = static_cast<uint32_t>(get_register(ra)); |
| 2114 double* p = reinterpret_cast<double*>(&ra_val); |
| 2115 set_d_register_from_double(frt, *p); |
| 2116 break; |
| 2117 } |
| 2118 #endif |
| 2119 default: { |
| 2120 found = false; |
| 2121 break; |
| 2122 } |
| 2123 } |
| 2124 |
| 2125 return found; |
| 2126 } |
| 2127 |
| 2128 |
| 2129 void Simulator::ExecuteExt2_9bit_part2(Instruction* instr) { |
| 2130 int opcode = instr->Bits(9, 1) << 1; |
| 2131 switch (opcode) { |
| 2132 case CNTLZWX: { |
| 2133 int rs = instr->RSValue(); |
| 2134 int ra = instr->RAValue(); |
| 2135 uintptr_t rs_val = get_register(rs); |
| 2136 uintptr_t count = 0; |
| 2137 int n = 0; |
| 2138 uintptr_t bit = 0x80000000; |
| 2139 for (; n < 32; n++) { |
| 2140 if (bit & rs_val) break; |
| 2141 count++; |
| 2142 bit >>= 1; |
| 2143 } |
| 2144 set_register(ra, count); |
| 2145 if (instr->Bit(0)) { // RC Bit set |
| 2146 int bf = 0; |
| 2147 if (count > 0) { |
| 2148 bf |= 0x40000000; |
| 2149 } |
| 2150 if (count == 0) { |
| 2151 bf |= 0x20000000; |
| 2152 } |
| 2153 condition_reg_ = (condition_reg_ & ~0xF0000000) | bf; |
| 2154 } |
| 2155 break; |
| 2156 } |
| 2157 #if V8_TARGET_ARCH_PPC64 |
| 2158 case CNTLZDX: { |
| 2159 int rs = instr->RSValue(); |
| 2160 int ra = instr->RAValue(); |
| 2161 uintptr_t rs_val = get_register(rs); |
| 2162 uintptr_t count = 0; |
| 2163 int n = 0; |
| 2164 uintptr_t bit = 0x8000000000000000UL; |
| 2165 for (; n < 64; n++) { |
| 2166 if (bit & rs_val) break; |
| 2167 count++; |
| 2168 bit >>= 1; |
| 2169 } |
| 2170 set_register(ra, count); |
| 2171 if (instr->Bit(0)) { // RC Bit set |
| 2172 int bf = 0; |
| 2173 if (count > 0) { |
| 2174 bf |= 0x40000000; |
| 2175 } |
| 2176 if (count == 0) { |
| 2177 bf |= 0x20000000; |
| 2178 } |
| 2179 condition_reg_ = (condition_reg_ & ~0xF0000000) | bf; |
| 2180 } |
| 2181 break; |
| 2182 } |
| 2183 #endif |
| 2184 case ANDX: { |
| 2185 int rs = instr->RSValue(); |
| 2186 int ra = instr->RAValue(); |
| 2187 int rb = instr->RBValue(); |
| 2188 intptr_t rs_val = get_register(rs); |
| 2189 intptr_t rb_val = get_register(rb); |
| 2190 intptr_t alu_out = rs_val & rb_val; |
| 2191 set_register(ra, alu_out); |
| 2192 if (instr->Bit(0)) { // RC Bit set |
| 2193 SetCR0(alu_out); |
| 2194 } |
| 2195 break; |
| 2196 } |
| 2197 case ANDCX: { |
| 2198 int rs = instr->RSValue(); |
| 2199 int ra = instr->RAValue(); |
| 2200 int rb = instr->RBValue(); |
| 2201 intptr_t rs_val = get_register(rs); |
| 2202 intptr_t rb_val = get_register(rb); |
| 2203 intptr_t alu_out = rs_val & ~rb_val; |
| 2204 set_register(ra, alu_out); |
| 2205 if (instr->Bit(0)) { // RC Bit set |
| 2206 SetCR0(alu_out); |
| 2207 } |
| 2208 break; |
| 2209 } |
| 2210 case CMPL: { |
| 2211 int ra = instr->RAValue(); |
| 2212 int rb = instr->RBValue(); |
| 2213 int cr = instr->Bits(25, 23); |
| 2214 uint32_t bf = 0; |
| 2215 #if V8_TARGET_ARCH_PPC64 |
| 2216 int L = instr->Bit(21); |
| 2217 if (L) { |
| 2218 #endif |
| 2219 uintptr_t ra_val = get_register(ra); |
| 2220 uintptr_t rb_val = get_register(rb); |
| 2221 if (ra_val < rb_val) { |
| 2222 bf |= 0x80000000; |
| 2223 } |
| 2224 if (ra_val > rb_val) { |
| 2225 bf |= 0x40000000; |
| 2226 } |
| 2227 if (ra_val == rb_val) { |
| 2228 bf |= 0x20000000; |
| 2229 } |
| 2230 #if V8_TARGET_ARCH_PPC64 |
| 2231 } else { |
| 2232 uint32_t ra_val = get_register(ra); |
| 2233 uint32_t rb_val = get_register(rb); |
| 2234 if (ra_val < rb_val) { |
| 2235 bf |= 0x80000000; |
| 2236 } |
| 2237 if (ra_val > rb_val) { |
| 2238 bf |= 0x40000000; |
| 2239 } |
| 2240 if (ra_val == rb_val) { |
| 2241 bf |= 0x20000000; |
| 2242 } |
| 2243 } |
| 2244 #endif |
| 2245 uint32_t condition_mask = 0xF0000000U >> (cr * 4); |
| 2246 uint32_t condition = bf >> (cr * 4); |
| 2247 condition_reg_ = (condition_reg_ & ~condition_mask) | condition; |
| 2248 break; |
| 2249 } |
| 2250 case SUBFX: { |
| 2251 int rt = instr->RTValue(); |
| 2252 int ra = instr->RAValue(); |
| 2253 int rb = instr->RBValue(); |
| 2254 // int oe = instr->Bit(10); |
| 2255 intptr_t ra_val = get_register(ra); |
| 2256 intptr_t rb_val = get_register(rb); |
| 2257 intptr_t alu_out = rb_val - ra_val; |
| 2258 // todo - figure out underflow |
| 2259 set_register(rt, alu_out); |
| 2260 if (instr->Bit(0)) { // RC Bit set |
| 2261 SetCR0(alu_out); |
| 2262 } |
| 2263 // todo - handle OE bit |
| 2264 break; |
| 2265 } |
| 2266 case ADDZEX: { |
| 2267 int rt = instr->RTValue(); |
| 2268 int ra = instr->RAValue(); |
| 2269 intptr_t ra_val = get_register(ra); |
| 2270 if (special_reg_xer_ & 0x20000000) { |
| 2271 ra_val += 1; |
| 2272 } |
| 2273 set_register(rt, ra_val); |
| 2274 if (instr->Bit(0)) { // RC bit set |
| 2275 SetCR0(ra_val); |
| 2276 } |
| 2277 // todo - handle OE bit |
| 2278 break; |
| 2279 } |
| 2280 case NORX: { |
| 2281 int rs = instr->RSValue(); |
| 2282 int ra = instr->RAValue(); |
| 2283 int rb = instr->RBValue(); |
| 2284 intptr_t rs_val = get_register(rs); |
| 2285 intptr_t rb_val = get_register(rb); |
| 2286 intptr_t alu_out = ~(rs_val | rb_val); |
| 2287 set_register(ra, alu_out); |
| 2288 if (instr->Bit(0)) { // RC bit set |
| 2289 SetCR0(alu_out); |
| 2290 } |
| 2291 break; |
| 2292 } |
| 2293 case MULLW: { |
| 2294 int rt = instr->RTValue(); |
| 2295 int ra = instr->RAValue(); |
| 2296 int rb = instr->RBValue(); |
| 2297 int32_t ra_val = (get_register(ra) & 0xFFFFFFFF); |
| 2298 int32_t rb_val = (get_register(rb) & 0xFFFFFFFF); |
| 2299 int32_t alu_out = ra_val * rb_val; |
| 2300 set_register(rt, alu_out); |
| 2301 if (instr->Bit(0)) { // RC bit set |
| 2302 SetCR0(alu_out); |
| 2303 } |
| 2304 // todo - handle OE bit |
| 2305 break; |
| 2306 } |
| 2307 #if V8_TARGET_ARCH_PPC64 |
| 2308 case MULLD: { |
| 2309 int rt = instr->RTValue(); |
| 2310 int ra = instr->RAValue(); |
| 2311 int rb = instr->RBValue(); |
| 2312 int64_t ra_val = get_register(ra); |
| 2313 int64_t rb_val = get_register(rb); |
| 2314 int64_t alu_out = ra_val * rb_val; |
| 2315 set_register(rt, alu_out); |
| 2316 if (instr->Bit(0)) { // RC bit set |
| 2317 SetCR0(alu_out); |
| 2318 } |
| 2319 // todo - handle OE bit |
| 2320 break; |
| 2321 } |
| 2322 #endif |
| 2323 case DIVW: { |
| 2324 int rt = instr->RTValue(); |
| 2325 int ra = instr->RAValue(); |
| 2326 int rb = instr->RBValue(); |
| 2327 int32_t ra_val = get_register(ra); |
| 2328 int32_t rb_val = get_register(rb); |
| 2329 bool overflow = (ra_val == kMinInt && rb_val == -1); |
| 2330 // result is undefined if divisor is zero or if operation |
| 2331 // is 0x80000000 / -1. |
| 2332 int32_t alu_out = (rb_val == 0 || overflow) ? -1 : ra_val / rb_val; |
| 2333 set_register(rt, alu_out); |
| 2334 if (instr->Bit(10)) { // OE bit set |
| 2335 if (overflow) { |
| 2336 special_reg_xer_ |= 0xC0000000; // set SO,OV |
| 2337 } else { |
| 2338 special_reg_xer_ &= ~0x40000000; // clear OV |
| 2339 } |
| 2340 } |
| 2341 if (instr->Bit(0)) { // RC bit set |
| 2342 bool setSO = (special_reg_xer_ & 0x80000000); |
| 2343 SetCR0(alu_out, setSO); |
| 2344 } |
| 2345 break; |
| 2346 } |
| 2347 #if V8_TARGET_ARCH_PPC64 |
| 2348 case DIVD: { |
| 2349 int rt = instr->RTValue(); |
| 2350 int ra = instr->RAValue(); |
| 2351 int rb = instr->RBValue(); |
| 2352 int64_t ra_val = get_register(ra); |
| 2353 int64_t rb_val = get_register(rb); |
| 2354 int64_t one = 1; // work-around gcc |
| 2355 int64_t kMinLongLong = (one << 63); |
| 2356 // result is undefined if divisor is zero or if operation |
| 2357 // is 0x80000000_00000000 / -1. |
| 2358 int64_t alu_out = |
| 2359 (rb_val == 0 || (ra_val == kMinLongLong && rb_val == -1)) |
| 2360 ? -1 |
| 2361 : ra_val / rb_val; |
| 2362 set_register(rt, alu_out); |
| 2363 if (instr->Bit(0)) { // RC bit set |
| 2364 SetCR0(alu_out); |
| 2365 } |
| 2366 // todo - handle OE bit |
| 2367 break; |
| 2368 } |
| 2369 #endif |
| 2370 case ADDX: { |
| 2371 int rt = instr->RTValue(); |
| 2372 int ra = instr->RAValue(); |
| 2373 int rb = instr->RBValue(); |
| 2374 // int oe = instr->Bit(10); |
| 2375 intptr_t ra_val = get_register(ra); |
| 2376 intptr_t rb_val = get_register(rb); |
| 2377 intptr_t alu_out = ra_val + rb_val; |
| 2378 set_register(rt, alu_out); |
| 2379 if (instr->Bit(0)) { // RC bit set |
| 2380 SetCR0(alu_out); |
| 2381 } |
| 2382 // todo - handle OE bit |
| 2383 break; |
| 2384 } |
| 2385 case XORX: { |
| 2386 int rs = instr->RSValue(); |
| 2387 int ra = instr->RAValue(); |
| 2388 int rb = instr->RBValue(); |
| 2389 intptr_t rs_val = get_register(rs); |
| 2390 intptr_t rb_val = get_register(rb); |
| 2391 intptr_t alu_out = rs_val ^ rb_val; |
| 2392 set_register(ra, alu_out); |
| 2393 if (instr->Bit(0)) { // RC bit set |
| 2394 SetCR0(alu_out); |
| 2395 } |
| 2396 break; |
| 2397 } |
| 2398 case ORX: { |
| 2399 int rs = instr->RSValue(); |
| 2400 int ra = instr->RAValue(); |
| 2401 int rb = instr->RBValue(); |
| 2402 intptr_t rs_val = get_register(rs); |
| 2403 intptr_t rb_val = get_register(rb); |
| 2404 intptr_t alu_out = rs_val | rb_val; |
| 2405 set_register(ra, alu_out); |
| 2406 if (instr->Bit(0)) { // RC bit set |
| 2407 SetCR0(alu_out); |
| 2408 } |
| 2409 break; |
| 2410 } |
| 2411 case MFSPR: { |
| 2412 int rt = instr->RTValue(); |
| 2413 int spr = instr->Bits(20, 11); |
| 2414 if (spr != 256) { |
| 2415 UNIMPLEMENTED(); // Only LRLR supported |
| 2416 } |
| 2417 set_register(rt, special_reg_lr_); |
| 2418 break; |
| 2419 } |
| 2420 case MTSPR: { |
| 2421 int rt = instr->RTValue(); |
| 2422 intptr_t rt_val = get_register(rt); |
| 2423 int spr = instr->Bits(20, 11); |
| 2424 if (spr == 256) { |
| 2425 special_reg_lr_ = rt_val; |
| 2426 } else if (spr == 288) { |
| 2427 special_reg_ctr_ = rt_val; |
| 2428 } else if (spr == 32) { |
| 2429 special_reg_xer_ = rt_val; |
| 2430 } else { |
| 2431 UNIMPLEMENTED(); // Only LR supported |
| 2432 } |
| 2433 break; |
| 2434 } |
| 2435 case MFCR: { |
| 2436 int rt = instr->RTValue(); |
| 2437 set_register(rt, condition_reg_); |
| 2438 break; |
| 2439 } |
| 2440 case STWUX: |
| 2441 case STWX: { |
| 2442 int rs = instr->RSValue(); |
| 2443 int ra = instr->RAValue(); |
| 2444 int rb = instr->RBValue(); |
| 2445 intptr_t ra_val = ra == 0 ? 0 : get_register(ra); |
| 2446 int32_t rs_val = get_register(rs); |
| 2447 intptr_t rb_val = get_register(rb); |
| 2448 WriteW(ra_val + rb_val, rs_val, instr); |
| 2449 if (opcode == STWUX) { |
| 2450 DCHECK(ra != 0); |
| 2451 set_register(ra, ra_val + rb_val); |
| 2452 } |
| 2453 break; |
| 2454 } |
| 2455 case STBUX: |
| 2456 case STBX: { |
| 2457 int rs = instr->RSValue(); |
| 2458 int ra = instr->RAValue(); |
| 2459 int rb = instr->RBValue(); |
| 2460 intptr_t ra_val = ra == 0 ? 0 : get_register(ra); |
| 2461 int8_t rs_val = get_register(rs); |
| 2462 intptr_t rb_val = get_register(rb); |
| 2463 WriteB(ra_val + rb_val, rs_val); |
| 2464 if (opcode == STBUX) { |
| 2465 DCHECK(ra != 0); |
| 2466 set_register(ra, ra_val + rb_val); |
| 2467 } |
| 2468 break; |
| 2469 } |
| 2470 case STHUX: |
| 2471 case STHX: { |
| 2472 int rs = instr->RSValue(); |
| 2473 int ra = instr->RAValue(); |
| 2474 int rb = instr->RBValue(); |
| 2475 intptr_t ra_val = ra == 0 ? 0 : get_register(ra); |
| 2476 int16_t rs_val = get_register(rs); |
| 2477 intptr_t rb_val = get_register(rb); |
| 2478 WriteH(ra_val + rb_val, rs_val, instr); |
| 2479 if (opcode == STHUX) { |
| 2480 DCHECK(ra != 0); |
| 2481 set_register(ra, ra_val + rb_val); |
| 2482 } |
| 2483 break; |
| 2484 } |
| 2485 case LWZX: |
| 2486 case LWZUX: { |
| 2487 int rt = instr->RTValue(); |
| 2488 int ra = instr->RAValue(); |
| 2489 int rb = instr->RBValue(); |
| 2490 intptr_t ra_val = ra == 0 ? 0 : get_register(ra); |
| 2491 intptr_t rb_val = get_register(rb); |
| 2492 set_register(rt, ReadWU(ra_val + rb_val, instr)); |
| 2493 if (opcode == LWZUX) { |
| 2494 DCHECK(ra != 0 && ra != rt); |
| 2495 set_register(ra, ra_val + rb_val); |
| 2496 } |
| 2497 break; |
| 2498 } |
| 2499 #if V8_TARGET_ARCH_PPC64 |
| 2500 case LDX: |
| 2501 case LDUX: { |
| 2502 int rt = instr->RTValue(); |
| 2503 int ra = instr->RAValue(); |
| 2504 int rb = instr->RBValue(); |
| 2505 intptr_t ra_val = ra == 0 ? 0 : get_register(ra); |
| 2506 intptr_t rb_val = get_register(rb); |
| 2507 intptr_t* result = ReadDW(ra_val + rb_val); |
| 2508 set_register(rt, *result); |
| 2509 if (opcode == LDUX) { |
| 2510 DCHECK(ra != 0 && ra != rt); |
| 2511 set_register(ra, ra_val + rb_val); |
| 2512 } |
| 2513 break; |
| 2514 } |
| 2515 case STDX: |
| 2516 case STDUX: { |
| 2517 int rs = instr->RSValue(); |
| 2518 int ra = instr->RAValue(); |
| 2519 int rb = instr->RBValue(); |
| 2520 intptr_t ra_val = ra == 0 ? 0 : get_register(ra); |
| 2521 intptr_t rs_val = get_register(rs); |
| 2522 intptr_t rb_val = get_register(rb); |
| 2523 WriteDW(ra_val + rb_val, rs_val); |
| 2524 if (opcode == STDUX) { |
| 2525 DCHECK(ra != 0); |
| 2526 set_register(ra, ra_val + rb_val); |
| 2527 } |
| 2528 break; |
| 2529 } |
| 2530 #endif |
| 2531 case LBZX: |
| 2532 case LBZUX: { |
| 2533 int rt = instr->RTValue(); |
| 2534 int ra = instr->RAValue(); |
| 2535 int rb = instr->RBValue(); |
| 2536 intptr_t ra_val = ra == 0 ? 0 : get_register(ra); |
| 2537 intptr_t rb_val = get_register(rb); |
| 2538 set_register(rt, ReadBU(ra_val + rb_val) & 0xFF); |
| 2539 if (opcode == LBZUX) { |
| 2540 DCHECK(ra != 0 && ra != rt); |
| 2541 set_register(ra, ra_val + rb_val); |
| 2542 } |
| 2543 break; |
| 2544 } |
| 2545 case LHZX: |
| 2546 case LHZUX: { |
| 2547 int rt = instr->RTValue(); |
| 2548 int ra = instr->RAValue(); |
| 2549 int rb = instr->RBValue(); |
| 2550 intptr_t ra_val = ra == 0 ? 0 : get_register(ra); |
| 2551 intptr_t rb_val = get_register(rb); |
| 2552 set_register(rt, ReadHU(ra_val + rb_val, instr) & 0xFFFF); |
| 2553 if (opcode == LHZUX) { |
| 2554 DCHECK(ra != 0 && ra != rt); |
| 2555 set_register(ra, ra_val + rb_val); |
| 2556 } |
| 2557 break; |
| 2558 } |
| 2559 case DCBF: { |
| 2560 // todo - simulate dcbf |
| 2561 break; |
| 2562 } |
| 2563 default: { |
| 2564 PrintF("Unimplemented: %08x\n", instr->InstructionBits()); |
| 2565 UNIMPLEMENTED(); // Not used by V8. |
| 2566 } |
| 2567 } |
| 2568 } |
| 2569 |
| 2570 |
| 2571 void Simulator::ExecuteExt2(Instruction* instr) { |
| 2572 // Check first the 10-1 bit versions |
| 2573 if (ExecuteExt2_10bit(instr)) return; |
| 2574 // Now look at the lesser encodings |
| 2575 if (ExecuteExt2_9bit_part1(instr)) return; |
| 2576 ExecuteExt2_9bit_part2(instr); |
| 2577 } |
| 2578 |
| 2579 |
| 2580 void Simulator::ExecuteExt4(Instruction* instr) { |
| 2581 switch (instr->Bits(5, 1) << 1) { |
| 2582 case FDIV: { |
| 2583 int frt = instr->RTValue(); |
| 2584 int fra = instr->RAValue(); |
| 2585 int frb = instr->RBValue(); |
| 2586 double fra_val = get_double_from_d_register(fra); |
| 2587 double frb_val = get_double_from_d_register(frb); |
| 2588 double frt_val = fra_val / frb_val; |
| 2589 set_d_register_from_double(frt, frt_val); |
| 2590 return; |
| 2591 } |
| 2592 case FSUB: { |
| 2593 int frt = instr->RTValue(); |
| 2594 int fra = instr->RAValue(); |
| 2595 int frb = instr->RBValue(); |
| 2596 double fra_val = get_double_from_d_register(fra); |
| 2597 double frb_val = get_double_from_d_register(frb); |
| 2598 double frt_val = fra_val - frb_val; |
| 2599 set_d_register_from_double(frt, frt_val); |
| 2600 return; |
| 2601 } |
| 2602 case FADD: { |
| 2603 int frt = instr->RTValue(); |
| 2604 int fra = instr->RAValue(); |
| 2605 int frb = instr->RBValue(); |
| 2606 double fra_val = get_double_from_d_register(fra); |
| 2607 double frb_val = get_double_from_d_register(frb); |
| 2608 double frt_val = fra_val + frb_val; |
| 2609 set_d_register_from_double(frt, frt_val); |
| 2610 return; |
| 2611 } |
| 2612 case FSQRT: { |
| 2613 int frt = instr->RTValue(); |
| 2614 int frb = instr->RBValue(); |
| 2615 double frb_val = get_double_from_d_register(frb); |
| 2616 double frt_val = std::sqrt(frb_val); |
| 2617 set_d_register_from_double(frt, frt_val); |
| 2618 return; |
| 2619 } |
| 2620 case FSEL: { |
| 2621 int frt = instr->RTValue(); |
| 2622 int fra = instr->RAValue(); |
| 2623 int frb = instr->RBValue(); |
| 2624 int frc = instr->RCValue(); |
| 2625 double fra_val = get_double_from_d_register(fra); |
| 2626 double frb_val = get_double_from_d_register(frb); |
| 2627 double frc_val = get_double_from_d_register(frc); |
| 2628 double frt_val = ((fra_val >= 0.0) ? frc_val : frb_val); |
| 2629 set_d_register_from_double(frt, frt_val); |
| 2630 return; |
| 2631 } |
| 2632 case FMUL: { |
| 2633 int frt = instr->RTValue(); |
| 2634 int fra = instr->RAValue(); |
| 2635 int frc = instr->RCValue(); |
| 2636 double fra_val = get_double_from_d_register(fra); |
| 2637 double frc_val = get_double_from_d_register(frc); |
| 2638 double frt_val = fra_val * frc_val; |
| 2639 set_d_register_from_double(frt, frt_val); |
| 2640 return; |
| 2641 } |
| 2642 case FMSUB: { |
| 2643 int frt = instr->RTValue(); |
| 2644 int fra = instr->RAValue(); |
| 2645 int frb = instr->RBValue(); |
| 2646 int frc = instr->RCValue(); |
| 2647 double fra_val = get_double_from_d_register(fra); |
| 2648 double frb_val = get_double_from_d_register(frb); |
| 2649 double frc_val = get_double_from_d_register(frc); |
| 2650 double frt_val = (fra_val * frc_val) - frb_val; |
| 2651 set_d_register_from_double(frt, frt_val); |
| 2652 return; |
| 2653 } |
| 2654 case FMADD: { |
| 2655 int frt = instr->RTValue(); |
| 2656 int fra = instr->RAValue(); |
| 2657 int frb = instr->RBValue(); |
| 2658 int frc = instr->RCValue(); |
| 2659 double fra_val = get_double_from_d_register(fra); |
| 2660 double frb_val = get_double_from_d_register(frb); |
| 2661 double frc_val = get_double_from_d_register(frc); |
| 2662 double frt_val = (fra_val * frc_val) + frb_val; |
| 2663 set_d_register_from_double(frt, frt_val); |
| 2664 return; |
| 2665 } |
| 2666 } |
| 2667 int opcode = instr->Bits(10, 1) << 1; |
| 2668 switch (opcode) { |
| 2669 case FCMPU: { |
| 2670 int fra = instr->RAValue(); |
| 2671 int frb = instr->RBValue(); |
| 2672 double fra_val = get_double_from_d_register(fra); |
| 2673 double frb_val = get_double_from_d_register(frb); |
| 2674 int cr = instr->Bits(25, 23); |
| 2675 int bf = 0; |
| 2676 if (fra_val < frb_val) { |
| 2677 bf |= 0x80000000; |
| 2678 } |
| 2679 if (fra_val > frb_val) { |
| 2680 bf |= 0x40000000; |
| 2681 } |
| 2682 if (fra_val == frb_val) { |
| 2683 bf |= 0x20000000; |
| 2684 } |
| 2685 if (std::isunordered(fra_val, frb_val)) { |
| 2686 bf |= 0x10000000; |
| 2687 } |
| 2688 int condition_mask = 0xF0000000 >> (cr * 4); |
| 2689 int condition = bf >> (cr * 4); |
| 2690 condition_reg_ = (condition_reg_ & ~condition_mask) | condition; |
| 2691 return; |
| 2692 } |
| 2693 case FRSP: { |
| 2694 int frt = instr->RTValue(); |
| 2695 int frb = instr->RBValue(); |
| 2696 double frb_val = get_double_from_d_register(frb); |
| 2697 // frsp round 8-byte double-precision value to 8-byte |
| 2698 // single-precision value, ignore the round here |
| 2699 set_d_register_from_double(frt, frb_val); |
| 2700 if (instr->Bit(0)) { // RC bit set |
| 2701 // UNIMPLEMENTED(); |
| 2702 } |
| 2703 return; |
| 2704 } |
| 2705 case FCFID: { |
| 2706 int frt = instr->RTValue(); |
| 2707 int frb = instr->RBValue(); |
| 2708 double t_val = get_double_from_d_register(frb); |
| 2709 int64_t* frb_val_p = reinterpret_cast<int64_t*>(&t_val); |
| 2710 double frt_val = static_cast<double>(*frb_val_p); |
| 2711 set_d_register_from_double(frt, frt_val); |
| 2712 return; |
| 2713 } |
| 2714 case FCTID: { |
| 2715 int frt = instr->RTValue(); |
| 2716 int frb = instr->RBValue(); |
| 2717 double frb_val = get_double_from_d_register(frb); |
| 2718 int64_t frt_val; |
| 2719 int64_t one = 1; // work-around gcc |
| 2720 int64_t kMinLongLong = (one << 63); |
| 2721 int64_t kMaxLongLong = kMinLongLong - 1; |
| 2722 |
| 2723 if (frb_val > kMaxLongLong) { |
| 2724 frt_val = kMaxLongLong; |
| 2725 } else if (frb_val < kMinLongLong) { |
| 2726 frt_val = kMinLongLong; |
| 2727 } else { |
| 2728 switch (fp_condition_reg_ & kFPRoundingModeMask) { |
| 2729 case kRoundToZero: |
| 2730 frt_val = (int64_t)frb_val; |
| 2731 break; |
| 2732 case kRoundToPlusInf: |
| 2733 frt_val = (int64_t)std::ceil(frb_val); |
| 2734 break; |
| 2735 case kRoundToMinusInf: |
| 2736 frt_val = (int64_t)std::floor(frb_val); |
| 2737 break; |
| 2738 default: |
| 2739 frt_val = (int64_t)frb_val; |
| 2740 UNIMPLEMENTED(); // Not used by V8. |
| 2741 break; |
| 2742 } |
| 2743 } |
| 2744 double* p = reinterpret_cast<double*>(&frt_val); |
| 2745 set_d_register_from_double(frt, *p); |
| 2746 return; |
| 2747 } |
| 2748 case FCTIDZ: { |
| 2749 int frt = instr->RTValue(); |
| 2750 int frb = instr->RBValue(); |
| 2751 double frb_val = get_double_from_d_register(frb); |
| 2752 int64_t frt_val; |
| 2753 int64_t one = 1; // work-around gcc |
| 2754 int64_t kMinLongLong = (one << 63); |
| 2755 int64_t kMaxLongLong = kMinLongLong - 1; |
| 2756 |
| 2757 if (frb_val > kMaxLongLong) { |
| 2758 frt_val = kMaxLongLong; |
| 2759 } else if (frb_val < kMinLongLong) { |
| 2760 frt_val = kMinLongLong; |
| 2761 } else { |
| 2762 frt_val = (int64_t)frb_val; |
| 2763 } |
| 2764 double* p = reinterpret_cast<double*>(&frt_val); |
| 2765 set_d_register_from_double(frt, *p); |
| 2766 return; |
| 2767 } |
| 2768 case FCTIW: |
| 2769 case FCTIWZ: { |
| 2770 int frt = instr->RTValue(); |
| 2771 int frb = instr->RBValue(); |
| 2772 double frb_val = get_double_from_d_register(frb); |
| 2773 int64_t frt_val; |
| 2774 if (frb_val > kMaxInt) { |
| 2775 frt_val = kMaxInt; |
| 2776 } else if (frb_val < kMinInt) { |
| 2777 frt_val = kMinInt; |
| 2778 } else { |
| 2779 if (opcode == FCTIWZ) { |
| 2780 frt_val = (int64_t)frb_val; |
| 2781 } else { |
| 2782 switch (fp_condition_reg_ & kFPRoundingModeMask) { |
| 2783 case kRoundToZero: |
| 2784 frt_val = (int64_t)frb_val; |
| 2785 break; |
| 2786 case kRoundToPlusInf: |
| 2787 frt_val = (int64_t)std::ceil(frb_val); |
| 2788 break; |
| 2789 case kRoundToMinusInf: |
| 2790 frt_val = (int64_t)std::floor(frb_val); |
| 2791 break; |
| 2792 case kRoundToNearest: |
| 2793 frt_val = (int64_t)lround(frb_val); |
| 2794 |
| 2795 // Round to even if exactly halfway. (lround rounds up) |
| 2796 if (std::fabs(static_cast<double>(frt_val) - frb_val) == 0.5 && |
| 2797 (frt_val % 2)) { |
| 2798 frt_val += ((frt_val > 0) ? -1 : 1); |
| 2799 } |
| 2800 |
| 2801 break; |
| 2802 default: |
| 2803 DCHECK(false); |
| 2804 frt_val = (int64_t)frb_val; |
| 2805 break; |
| 2806 } |
| 2807 } |
| 2808 } |
| 2809 double* p = reinterpret_cast<double*>(&frt_val); |
| 2810 set_d_register_from_double(frt, *p); |
| 2811 return; |
| 2812 } |
| 2813 case FNEG: { |
| 2814 int frt = instr->RTValue(); |
| 2815 int frb = instr->RBValue(); |
| 2816 double frb_val = get_double_from_d_register(frb); |
| 2817 double frt_val = -frb_val; |
| 2818 set_d_register_from_double(frt, frt_val); |
| 2819 return; |
| 2820 } |
| 2821 case FMR: { |
| 2822 int frt = instr->RTValue(); |
| 2823 int frb = instr->RBValue(); |
| 2824 double frb_val = get_double_from_d_register(frb); |
| 2825 double frt_val = frb_val; |
| 2826 set_d_register_from_double(frt, frt_val); |
| 2827 return; |
| 2828 } |
| 2829 case MTFSFI: { |
| 2830 int bf = instr->Bits(25, 23); |
| 2831 int imm = instr->Bits(15, 12); |
| 2832 int fp_condition_mask = 0xF0000000 >> (bf * 4); |
| 2833 fp_condition_reg_ &= ~fp_condition_mask; |
| 2834 fp_condition_reg_ |= (imm << (28 - (bf * 4))); |
| 2835 if (instr->Bit(0)) { // RC bit set |
| 2836 condition_reg_ &= 0xF0FFFFFF; |
| 2837 condition_reg_ |= (imm << 23); |
| 2838 } |
| 2839 return; |
| 2840 } |
| 2841 case MTFSF: { |
| 2842 int frb = instr->RBValue(); |
| 2843 double frb_dval = get_double_from_d_register(frb); |
| 2844 int64_t* p = reinterpret_cast<int64_t*>(&frb_dval); |
| 2845 int32_t frb_ival = static_cast<int32_t>((*p) & 0xffffffff); |
| 2846 int l = instr->Bits(25, 25); |
| 2847 if (l == 1) { |
| 2848 fp_condition_reg_ = frb_ival; |
| 2849 } else { |
| 2850 UNIMPLEMENTED(); |
| 2851 } |
| 2852 if (instr->Bit(0)) { // RC bit set |
| 2853 UNIMPLEMENTED(); |
| 2854 // int w = instr->Bits(16, 16); |
| 2855 // int flm = instr->Bits(24, 17); |
| 2856 } |
| 2857 return; |
| 2858 } |
| 2859 case MFFS: { |
| 2860 int frt = instr->RTValue(); |
| 2861 int64_t lval = static_cast<int64_t>(fp_condition_reg_); |
| 2862 double* p = reinterpret_cast<double*>(&lval); |
| 2863 set_d_register_from_double(frt, *p); |
| 2864 return; |
| 2865 } |
| 2866 case FABS: { |
| 2867 int frt = instr->RTValue(); |
| 2868 int frb = instr->RBValue(); |
| 2869 double frb_val = get_double_from_d_register(frb); |
| 2870 double frt_val = std::fabs(frb_val); |
| 2871 set_d_register_from_double(frt, frt_val); |
| 2872 return; |
| 2873 } |
| 2874 case FRIM: { |
| 2875 int frt = instr->RTValue(); |
| 2876 int frb = instr->RBValue(); |
| 2877 double frb_val = get_double_from_d_register(frb); |
| 2878 int64_t floor_val = (int64_t)frb_val; |
| 2879 if (floor_val > frb_val) floor_val--; |
| 2880 double frt_val = static_cast<double>(floor_val); |
| 2881 set_d_register_from_double(frt, frt_val); |
| 2882 return; |
| 2883 } |
| 2884 } |
| 2885 UNIMPLEMENTED(); // Not used by V8. |
| 2886 } |
| 2887 |
| 2888 #if V8_TARGET_ARCH_PPC64 |
| 2889 void Simulator::ExecuteExt5(Instruction* instr) { |
| 2890 switch (instr->Bits(4, 2) << 2) { |
| 2891 case RLDICL: { |
| 2892 int ra = instr->RAValue(); |
| 2893 int rs = instr->RSValue(); |
| 2894 uintptr_t rs_val = get_register(rs); |
| 2895 int sh = (instr->Bits(15, 11) | (instr->Bit(1) << 5)); |
| 2896 int mb = (instr->Bits(10, 6) | (instr->Bit(5) << 5)); |
| 2897 DCHECK(sh >= 0 && sh <= 63); |
| 2898 DCHECK(mb >= 0 && mb <= 63); |
| 2899 // rotate left |
| 2900 uintptr_t result = (rs_val << sh) | (rs_val >> (64 - sh)); |
| 2901 uintptr_t mask = 0xffffffffffffffff >> mb; |
| 2902 result &= mask; |
| 2903 set_register(ra, result); |
| 2904 if (instr->Bit(0)) { // RC bit set |
| 2905 SetCR0(result); |
| 2906 } |
| 2907 return; |
| 2908 } |
| 2909 case RLDICR: { |
| 2910 int ra = instr->RAValue(); |
| 2911 int rs = instr->RSValue(); |
| 2912 uintptr_t rs_val = get_register(rs); |
| 2913 int sh = (instr->Bits(15, 11) | (instr->Bit(1) << 5)); |
| 2914 int me = (instr->Bits(10, 6) | (instr->Bit(5) << 5)); |
| 2915 DCHECK(sh >= 0 && sh <= 63); |
| 2916 DCHECK(me >= 0 && me <= 63); |
| 2917 // rotate left |
| 2918 uintptr_t result = (rs_val << sh) | (rs_val >> (64 - sh)); |
| 2919 uintptr_t mask = 0xffffffffffffffff << (63 - me); |
| 2920 result &= mask; |
| 2921 set_register(ra, result); |
| 2922 if (instr->Bit(0)) { // RC bit set |
| 2923 SetCR0(result); |
| 2924 } |
| 2925 return; |
| 2926 } |
| 2927 case RLDIC: { |
| 2928 int ra = instr->RAValue(); |
| 2929 int rs = instr->RSValue(); |
| 2930 uintptr_t rs_val = get_register(rs); |
| 2931 int sh = (instr->Bits(15, 11) | (instr->Bit(1) << 5)); |
| 2932 int mb = (instr->Bits(10, 6) | (instr->Bit(5) << 5)); |
| 2933 DCHECK(sh >= 0 && sh <= 63); |
| 2934 DCHECK(mb >= 0 && mb <= 63); |
| 2935 // rotate left |
| 2936 uintptr_t result = (rs_val << sh) | (rs_val >> (64 - sh)); |
| 2937 uintptr_t mask = (0xffffffffffffffff >> mb) & (0xffffffffffffffff << sh); |
| 2938 result &= mask; |
| 2939 set_register(ra, result); |
| 2940 if (instr->Bit(0)) { // RC bit set |
| 2941 SetCR0(result); |
| 2942 } |
| 2943 return; |
| 2944 } |
| 2945 case RLDIMI: { |
| 2946 int ra = instr->RAValue(); |
| 2947 int rs = instr->RSValue(); |
| 2948 uintptr_t rs_val = get_register(rs); |
| 2949 intptr_t ra_val = get_register(ra); |
| 2950 int sh = (instr->Bits(15, 11) | (instr->Bit(1) << 5)); |
| 2951 int mb = (instr->Bits(10, 6) | (instr->Bit(5) << 5)); |
| 2952 int me = 63 - sh; |
| 2953 // rotate left |
| 2954 uintptr_t result = (rs_val << sh) | (rs_val >> (64 - sh)); |
| 2955 uintptr_t mask = 0; |
| 2956 if (mb < me + 1) { |
| 2957 uintptr_t bit = 0x8000000000000000 >> mb; |
| 2958 for (; mb <= me; mb++) { |
| 2959 mask |= bit; |
| 2960 bit >>= 1; |
| 2961 } |
| 2962 } else if (mb == me + 1) { |
| 2963 mask = 0xffffffffffffffff; |
| 2964 } else { // mb > me+1 |
| 2965 uintptr_t bit = 0x8000000000000000 >> (me + 1); // needs to be tested |
| 2966 mask = 0xffffffffffffffff; |
| 2967 for (; me < mb; me++) { |
| 2968 mask ^= bit; |
| 2969 bit >>= 1; |
| 2970 } |
| 2971 } |
| 2972 result &= mask; |
| 2973 ra_val &= ~mask; |
| 2974 result |= ra_val; |
| 2975 set_register(ra, result); |
| 2976 if (instr->Bit(0)) { // RC bit set |
| 2977 SetCR0(result); |
| 2978 } |
| 2979 return; |
| 2980 } |
| 2981 } |
| 2982 switch (instr->Bits(4, 1) << 1) { |
| 2983 case RLDCL: { |
| 2984 int ra = instr->RAValue(); |
| 2985 int rs = instr->RSValue(); |
| 2986 int rb = instr->RBValue(); |
| 2987 uintptr_t rs_val = get_register(rs); |
| 2988 uintptr_t rb_val = get_register(rb); |
| 2989 int sh = (rb_val & 0x3f); |
| 2990 int mb = (instr->Bits(10, 6) | (instr->Bit(5) << 5)); |
| 2991 DCHECK(sh >= 0 && sh <= 63); |
| 2992 DCHECK(mb >= 0 && mb <= 63); |
| 2993 // rotate left |
| 2994 uintptr_t result = (rs_val << sh) | (rs_val >> (64 - sh)); |
| 2995 uintptr_t mask = 0xffffffffffffffff >> mb; |
| 2996 result &= mask; |
| 2997 set_register(ra, result); |
| 2998 if (instr->Bit(0)) { // RC bit set |
| 2999 SetCR0(result); |
| 3000 } |
| 3001 return; |
| 3002 } |
| 3003 } |
| 3004 UNIMPLEMENTED(); // Not used by V8. |
| 3005 } |
| 3006 #endif |
| 3007 |
| 3008 |
| 3009 void Simulator::ExecuteGeneric(Instruction* instr) { |
| 3010 int opcode = instr->OpcodeValue() << 26; |
| 3011 switch (opcode) { |
| 3012 case SUBFIC: { |
| 3013 int rt = instr->RTValue(); |
| 3014 int ra = instr->RAValue(); |
| 3015 intptr_t ra_val = get_register(ra); |
| 3016 int32_t im_val = instr->Bits(15, 0); |
| 3017 im_val = SIGN_EXT_IMM16(im_val); |
| 3018 intptr_t alu_out = im_val - ra_val; |
| 3019 set_register(rt, alu_out); |
| 3020 // todo - handle RC bit |
| 3021 break; |
| 3022 } |
| 3023 case CMPLI: { |
| 3024 int ra = instr->RAValue(); |
| 3025 uint32_t im_val = instr->Bits(15, 0); |
| 3026 int cr = instr->Bits(25, 23); |
| 3027 uint32_t bf = 0; |
| 3028 #if V8_TARGET_ARCH_PPC64 |
| 3029 int L = instr->Bit(21); |
| 3030 if (L) { |
| 3031 #endif |
| 3032 uintptr_t ra_val = get_register(ra); |
| 3033 if (ra_val < im_val) { |
| 3034 bf |= 0x80000000; |
| 3035 } |
| 3036 if (ra_val > im_val) { |
| 3037 bf |= 0x40000000; |
| 3038 } |
| 3039 if (ra_val == im_val) { |
| 3040 bf |= 0x20000000; |
| 3041 } |
| 3042 #if V8_TARGET_ARCH_PPC64 |
| 3043 } else { |
| 3044 uint32_t ra_val = get_register(ra); |
| 3045 if (ra_val < im_val) { |
| 3046 bf |= 0x80000000; |
| 3047 } |
| 3048 if (ra_val > im_val) { |
| 3049 bf |= 0x40000000; |
| 3050 } |
| 3051 if (ra_val == im_val) { |
| 3052 bf |= 0x20000000; |
| 3053 } |
| 3054 } |
| 3055 #endif |
| 3056 uint32_t condition_mask = 0xF0000000U >> (cr * 4); |
| 3057 uint32_t condition = bf >> (cr * 4); |
| 3058 condition_reg_ = (condition_reg_ & ~condition_mask) | condition; |
| 3059 break; |
| 3060 } |
| 3061 case CMPI: { |
| 3062 int ra = instr->RAValue(); |
| 3063 int32_t im_val = instr->Bits(15, 0); |
| 3064 im_val = SIGN_EXT_IMM16(im_val); |
| 3065 int cr = instr->Bits(25, 23); |
| 3066 uint32_t bf = 0; |
| 3067 #if V8_TARGET_ARCH_PPC64 |
| 3068 int L = instr->Bit(21); |
| 3069 if (L) { |
| 3070 #endif |
| 3071 intptr_t ra_val = get_register(ra); |
| 3072 if (ra_val < im_val) { |
| 3073 bf |= 0x80000000; |
| 3074 } |
| 3075 if (ra_val > im_val) { |
| 3076 bf |= 0x40000000; |
| 3077 } |
| 3078 if (ra_val == im_val) { |
| 3079 bf |= 0x20000000; |
| 3080 } |
| 3081 #if V8_TARGET_ARCH_PPC64 |
| 3082 } else { |
| 3083 int32_t ra_val = get_register(ra); |
| 3084 if (ra_val < im_val) { |
| 3085 bf |= 0x80000000; |
| 3086 } |
| 3087 if (ra_val > im_val) { |
| 3088 bf |= 0x40000000; |
| 3089 } |
| 3090 if (ra_val == im_val) { |
| 3091 bf |= 0x20000000; |
| 3092 } |
| 3093 } |
| 3094 #endif |
| 3095 uint32_t condition_mask = 0xF0000000U >> (cr * 4); |
| 3096 uint32_t condition = bf >> (cr * 4); |
| 3097 condition_reg_ = (condition_reg_ & ~condition_mask) | condition; |
| 3098 break; |
| 3099 } |
| 3100 case ADDIC: { |
| 3101 int rt = instr->RTValue(); |
| 3102 int ra = instr->RAValue(); |
| 3103 uintptr_t ra_val = get_register(ra); |
| 3104 uintptr_t im_val = SIGN_EXT_IMM16(instr->Bits(15, 0)); |
| 3105 uintptr_t alu_out = ra_val + im_val; |
| 3106 // Check overflow |
| 3107 if (~ra_val < im_val) { |
| 3108 special_reg_xer_ = (special_reg_xer_ & ~0xF0000000) | 0x20000000; |
| 3109 } else { |
| 3110 special_reg_xer_ &= ~0xF0000000; |
| 3111 } |
| 3112 set_register(rt, alu_out); |
| 3113 break; |
| 3114 } |
| 3115 case ADDI: { |
| 3116 int rt = instr->RTValue(); |
| 3117 int ra = instr->RAValue(); |
| 3118 int32_t im_val = SIGN_EXT_IMM16(instr->Bits(15, 0)); |
| 3119 intptr_t alu_out; |
| 3120 if (ra == 0) { |
| 3121 alu_out = im_val; |
| 3122 } else { |
| 3123 intptr_t ra_val = get_register(ra); |
| 3124 alu_out = ra_val + im_val; |
| 3125 } |
| 3126 set_register(rt, alu_out); |
| 3127 // todo - handle RC bit |
| 3128 break; |
| 3129 } |
| 3130 case ADDIS: { |
| 3131 int rt = instr->RTValue(); |
| 3132 int ra = instr->RAValue(); |
| 3133 int32_t im_val = (instr->Bits(15, 0) << 16); |
| 3134 intptr_t alu_out; |
| 3135 if (ra == 0) { // treat r0 as zero |
| 3136 alu_out = im_val; |
| 3137 } else { |
| 3138 intptr_t ra_val = get_register(ra); |
| 3139 alu_out = ra_val + im_val; |
| 3140 } |
| 3141 set_register(rt, alu_out); |
| 3142 break; |
| 3143 } |
| 3144 case BCX: { |
| 3145 ExecuteBranchConditional(instr); |
| 3146 break; |
| 3147 } |
| 3148 case BX: { |
| 3149 int offset = (instr->Bits(25, 2) << 8) >> 6; |
| 3150 if (instr->Bit(0) == 1) { // LK flag set |
| 3151 special_reg_lr_ = get_pc() + 4; |
| 3152 } |
| 3153 set_pc(get_pc() + offset); |
| 3154 // todo - AA flag |
| 3155 break; |
| 3156 } |
| 3157 case EXT1: { |
| 3158 ExecuteExt1(instr); |
| 3159 break; |
| 3160 } |
| 3161 case RLWIMIX: { |
| 3162 int ra = instr->RAValue(); |
| 3163 int rs = instr->RSValue(); |
| 3164 uint32_t rs_val = get_register(rs); |
| 3165 int32_t ra_val = get_register(ra); |
| 3166 int sh = instr->Bits(15, 11); |
| 3167 int mb = instr->Bits(10, 6); |
| 3168 int me = instr->Bits(5, 1); |
| 3169 // rotate left |
| 3170 uint32_t result = (rs_val << sh) | (rs_val >> (32 - sh)); |
| 3171 int mask = 0; |
| 3172 if (mb < me + 1) { |
| 3173 int bit = 0x80000000 >> mb; |
| 3174 for (; mb <= me; mb++) { |
| 3175 mask |= bit; |
| 3176 bit >>= 1; |
| 3177 } |
| 3178 } else if (mb == me + 1) { |
| 3179 mask = 0xffffffff; |
| 3180 } else { // mb > me+1 |
| 3181 int bit = 0x80000000 >> (me + 1); // needs to be tested |
| 3182 mask = 0xffffffff; |
| 3183 for (; me < mb; me++) { |
| 3184 mask ^= bit; |
| 3185 bit >>= 1; |
| 3186 } |
| 3187 } |
| 3188 result &= mask; |
| 3189 ra_val &= ~mask; |
| 3190 result |= ra_val; |
| 3191 set_register(ra, result); |
| 3192 if (instr->Bit(0)) { // RC bit set |
| 3193 SetCR0(result); |
| 3194 } |
| 3195 break; |
| 3196 } |
| 3197 case RLWINMX: |
| 3198 case RLWNMX: { |
| 3199 int ra = instr->RAValue(); |
| 3200 int rs = instr->RSValue(); |
| 3201 uint32_t rs_val = get_register(rs); |
| 3202 int sh = 0; |
| 3203 if (opcode == RLWINMX) { |
| 3204 sh = instr->Bits(15, 11); |
| 3205 } else { |
| 3206 int rb = instr->RBValue(); |
| 3207 uint32_t rb_val = get_register(rb); |
| 3208 sh = (rb_val & 0x1f); |
| 3209 } |
| 3210 int mb = instr->Bits(10, 6); |
| 3211 int me = instr->Bits(5, 1); |
| 3212 // rotate left |
| 3213 uint32_t result = (rs_val << sh) | (rs_val >> (32 - sh)); |
| 3214 int mask = 0; |
| 3215 if (mb < me + 1) { |
| 3216 int bit = 0x80000000 >> mb; |
| 3217 for (; mb <= me; mb++) { |
| 3218 mask |= bit; |
| 3219 bit >>= 1; |
| 3220 } |
| 3221 } else if (mb == me + 1) { |
| 3222 mask = 0xffffffff; |
| 3223 } else { // mb > me+1 |
| 3224 int bit = 0x80000000 >> (me + 1); // needs to be tested |
| 3225 mask = 0xffffffff; |
| 3226 for (; me < mb; me++) { |
| 3227 mask ^= bit; |
| 3228 bit >>= 1; |
| 3229 } |
| 3230 } |
| 3231 result &= mask; |
| 3232 set_register(ra, result); |
| 3233 if (instr->Bit(0)) { // RC bit set |
| 3234 SetCR0(result); |
| 3235 } |
| 3236 break; |
| 3237 } |
| 3238 case ORI: { |
| 3239 int rs = instr->RSValue(); |
| 3240 int ra = instr->RAValue(); |
| 3241 intptr_t rs_val = get_register(rs); |
| 3242 uint32_t im_val = instr->Bits(15, 0); |
| 3243 intptr_t alu_out = rs_val | im_val; |
| 3244 set_register(ra, alu_out); |
| 3245 break; |
| 3246 } |
| 3247 case ORIS: { |
| 3248 int rs = instr->RSValue(); |
| 3249 int ra = instr->RAValue(); |
| 3250 intptr_t rs_val = get_register(rs); |
| 3251 uint32_t im_val = instr->Bits(15, 0); |
| 3252 intptr_t alu_out = rs_val | (im_val << 16); |
| 3253 set_register(ra, alu_out); |
| 3254 break; |
| 3255 } |
| 3256 case XORI: { |
| 3257 int rs = instr->RSValue(); |
| 3258 int ra = instr->RAValue(); |
| 3259 intptr_t rs_val = get_register(rs); |
| 3260 uint32_t im_val = instr->Bits(15, 0); |
| 3261 intptr_t alu_out = rs_val ^ im_val; |
| 3262 set_register(ra, alu_out); |
| 3263 // todo - set condition based SO bit |
| 3264 break; |
| 3265 } |
| 3266 case XORIS: { |
| 3267 int rs = instr->RSValue(); |
| 3268 int ra = instr->RAValue(); |
| 3269 intptr_t rs_val = get_register(rs); |
| 3270 uint32_t im_val = instr->Bits(15, 0); |
| 3271 intptr_t alu_out = rs_val ^ (im_val << 16); |
| 3272 set_register(ra, alu_out); |
| 3273 break; |
| 3274 } |
| 3275 case ANDIx: { |
| 3276 int rs = instr->RSValue(); |
| 3277 int ra = instr->RAValue(); |
| 3278 intptr_t rs_val = get_register(rs); |
| 3279 uint32_t im_val = instr->Bits(15, 0); |
| 3280 intptr_t alu_out = rs_val & im_val; |
| 3281 set_register(ra, alu_out); |
| 3282 SetCR0(alu_out); |
| 3283 break; |
| 3284 } |
| 3285 case ANDISx: { |
| 3286 int rs = instr->RSValue(); |
| 3287 int ra = instr->RAValue(); |
| 3288 intptr_t rs_val = get_register(rs); |
| 3289 uint32_t im_val = instr->Bits(15, 0); |
| 3290 intptr_t alu_out = rs_val & (im_val << 16); |
| 3291 set_register(ra, alu_out); |
| 3292 SetCR0(alu_out); |
| 3293 break; |
| 3294 } |
| 3295 case EXT2: { |
| 3296 ExecuteExt2(instr); |
| 3297 break; |
| 3298 } |
| 3299 |
| 3300 case LWZU: |
| 3301 case LWZ: { |
| 3302 int ra = instr->RAValue(); |
| 3303 int rt = instr->RTValue(); |
| 3304 intptr_t ra_val = ra == 0 ? 0 : get_register(ra); |
| 3305 int offset = SIGN_EXT_IMM16(instr->Bits(15, 0)); |
| 3306 set_register(rt, ReadWU(ra_val + offset, instr)); |
| 3307 if (opcode == LWZU) { |
| 3308 DCHECK(ra != 0); |
| 3309 set_register(ra, ra_val + offset); |
| 3310 } |
| 3311 break; |
| 3312 } |
| 3313 |
| 3314 case LBZU: |
| 3315 case LBZ: { |
| 3316 int ra = instr->RAValue(); |
| 3317 int rt = instr->RTValue(); |
| 3318 intptr_t ra_val = ra == 0 ? 0 : get_register(ra); |
| 3319 int offset = SIGN_EXT_IMM16(instr->Bits(15, 0)); |
| 3320 set_register(rt, ReadB(ra_val + offset) & 0xFF); |
| 3321 if (opcode == LBZU) { |
| 3322 DCHECK(ra != 0); |
| 3323 set_register(ra, ra_val + offset); |
| 3324 } |
| 3325 break; |
| 3326 } |
| 3327 |
| 3328 case STWU: |
| 3329 case STW: { |
| 3330 int ra = instr->RAValue(); |
| 3331 int rs = instr->RSValue(); |
| 3332 intptr_t ra_val = ra == 0 ? 0 : get_register(ra); |
| 3333 int32_t rs_val = get_register(rs); |
| 3334 int offset = SIGN_EXT_IMM16(instr->Bits(15, 0)); |
| 3335 WriteW(ra_val + offset, rs_val, instr); |
| 3336 if (opcode == STWU) { |
| 3337 DCHECK(ra != 0); |
| 3338 set_register(ra, ra_val + offset); |
| 3339 } |
| 3340 // printf("r%d %08x -> %08x\n", rs, rs_val, offset); // 0xdead |
| 3341 break; |
| 3342 } |
| 3343 |
| 3344 case STBU: |
| 3345 case STB: { |
| 3346 int ra = instr->RAValue(); |
| 3347 int rs = instr->RSValue(); |
| 3348 intptr_t ra_val = ra == 0 ? 0 : get_register(ra); |
| 3349 int8_t rs_val = get_register(rs); |
| 3350 int offset = SIGN_EXT_IMM16(instr->Bits(15, 0)); |
| 3351 WriteB(ra_val + offset, rs_val); |
| 3352 if (opcode == STBU) { |
| 3353 DCHECK(ra != 0); |
| 3354 set_register(ra, ra_val + offset); |
| 3355 } |
| 3356 break; |
| 3357 } |
| 3358 |
| 3359 case LHZU: |
| 3360 case LHZ: { |
| 3361 int ra = instr->RAValue(); |
| 3362 int rt = instr->RTValue(); |
| 3363 intptr_t ra_val = ra == 0 ? 0 : get_register(ra); |
| 3364 int offset = SIGN_EXT_IMM16(instr->Bits(15, 0)); |
| 3365 uintptr_t result = ReadHU(ra_val + offset, instr) & 0xffff; |
| 3366 set_register(rt, result); |
| 3367 if (opcode == LHZU) { |
| 3368 DCHECK(ra != 0); |
| 3369 set_register(ra, ra_val + offset); |
| 3370 } |
| 3371 break; |
| 3372 } |
| 3373 |
| 3374 case LHA: |
| 3375 case LHAU: { |
| 3376 UNIMPLEMENTED(); |
| 3377 break; |
| 3378 } |
| 3379 |
| 3380 case STHU: |
| 3381 case STH: { |
| 3382 int ra = instr->RAValue(); |
| 3383 int rs = instr->RSValue(); |
| 3384 intptr_t ra_val = ra == 0 ? 0 : get_register(ra); |
| 3385 int16_t rs_val = get_register(rs); |
| 3386 int offset = SIGN_EXT_IMM16(instr->Bits(15, 0)); |
| 3387 WriteH(ra_val + offset, rs_val, instr); |
| 3388 if (opcode == STHU) { |
| 3389 DCHECK(ra != 0); |
| 3390 set_register(ra, ra_val + offset); |
| 3391 } |
| 3392 break; |
| 3393 } |
| 3394 |
| 3395 case LMW: |
| 3396 case STMW: { |
| 3397 UNIMPLEMENTED(); |
| 3398 break; |
| 3399 } |
| 3400 |
| 3401 case LFSU: |
| 3402 case LFS: { |
| 3403 int frt = instr->RTValue(); |
| 3404 int ra = instr->RAValue(); |
| 3405 int32_t offset = SIGN_EXT_IMM16(instr->Bits(15, 0)); |
| 3406 intptr_t ra_val = ra == 0 ? 0 : get_register(ra); |
| 3407 int32_t val = ReadW(ra_val + offset, instr); |
| 3408 float* fptr = reinterpret_cast<float*>(&val); |
| 3409 set_d_register_from_double(frt, static_cast<double>(*fptr)); |
| 3410 if (opcode == LFSU) { |
| 3411 DCHECK(ra != 0); |
| 3412 set_register(ra, ra_val + offset); |
| 3413 } |
| 3414 break; |
| 3415 } |
| 3416 |
| 3417 case LFDU: |
| 3418 case LFD: { |
| 3419 int frt = instr->RTValue(); |
| 3420 int ra = instr->RAValue(); |
| 3421 int32_t offset = SIGN_EXT_IMM16(instr->Bits(15, 0)); |
| 3422 intptr_t ra_val = ra == 0 ? 0 : get_register(ra); |
| 3423 double* dptr = reinterpret_cast<double*>(ReadDW(ra_val + offset)); |
| 3424 set_d_register_from_double(frt, *dptr); |
| 3425 if (opcode == LFDU) { |
| 3426 DCHECK(ra != 0); |
| 3427 set_register(ra, ra_val + offset); |
| 3428 } |
| 3429 break; |
| 3430 } |
| 3431 |
| 3432 case STFSU: { |
| 3433 case STFS: |
| 3434 int frs = instr->RSValue(); |
| 3435 int ra = instr->RAValue(); |
| 3436 int32_t offset = SIGN_EXT_IMM16(instr->Bits(15, 0)); |
| 3437 intptr_t ra_val = ra == 0 ? 0 : get_register(ra); |
| 3438 float frs_val = static_cast<float>(get_double_from_d_register(frs)); |
| 3439 int32_t* p = reinterpret_cast<int32_t*>(&frs_val); |
| 3440 WriteW(ra_val + offset, *p, instr); |
| 3441 if (opcode == STFSU) { |
| 3442 DCHECK(ra != 0); |
| 3443 set_register(ra, ra_val + offset); |
| 3444 } |
| 3445 break; |
| 3446 } |
| 3447 |
| 3448 case STFDU: |
| 3449 case STFD: { |
| 3450 int frs = instr->RSValue(); |
| 3451 int ra = instr->RAValue(); |
| 3452 int32_t offset = SIGN_EXT_IMM16(instr->Bits(15, 0)); |
| 3453 intptr_t ra_val = ra == 0 ? 0 : get_register(ra); |
| 3454 double frs_val = get_double_from_d_register(frs); |
| 3455 int64_t* p = reinterpret_cast<int64_t*>(&frs_val); |
| 3456 WriteDW(ra_val + offset, *p); |
| 3457 if (opcode == STFDU) { |
| 3458 DCHECK(ra != 0); |
| 3459 set_register(ra, ra_val + offset); |
| 3460 } |
| 3461 break; |
| 3462 } |
| 3463 |
| 3464 case EXT3: |
| 3465 UNIMPLEMENTED(); |
| 3466 case EXT4: { |
| 3467 ExecuteExt4(instr); |
| 3468 break; |
| 3469 } |
| 3470 |
| 3471 #if V8_TARGET_ARCH_PPC64 |
| 3472 case EXT5: { |
| 3473 ExecuteExt5(instr); |
| 3474 break; |
| 3475 } |
| 3476 case LD: { |
| 3477 int ra = instr->RAValue(); |
| 3478 int rt = instr->RTValue(); |
| 3479 int64_t ra_val = ra == 0 ? 0 : get_register(ra); |
| 3480 int offset = SIGN_EXT_IMM16(instr->Bits(15, 0) & ~3); |
| 3481 switch (instr->Bits(1, 0)) { |
| 3482 case 0: { // ld |
| 3483 intptr_t* result = ReadDW(ra_val + offset); |
| 3484 set_register(rt, *result); |
| 3485 break; |
| 3486 } |
| 3487 case 1: { // ldu |
| 3488 intptr_t* result = ReadDW(ra_val + offset); |
| 3489 set_register(rt, *result); |
| 3490 DCHECK(ra != 0); |
| 3491 set_register(ra, ra_val + offset); |
| 3492 break; |
| 3493 } |
| 3494 case 2: { // lwa |
| 3495 intptr_t result = ReadW(ra_val + offset, instr); |
| 3496 set_register(rt, result); |
| 3497 break; |
| 3498 } |
| 3499 } |
| 3500 break; |
| 3501 } |
| 3502 |
| 3503 case STD: { |
| 3504 int ra = instr->RAValue(); |
| 3505 int rs = instr->RSValue(); |
| 3506 int64_t ra_val = ra == 0 ? 0 : get_register(ra); |
| 3507 int64_t rs_val = get_register(rs); |
| 3508 int offset = SIGN_EXT_IMM16(instr->Bits(15, 0) & ~3); |
| 3509 WriteDW(ra_val + offset, rs_val); |
| 3510 if (instr->Bit(0) == 1) { // This is the STDU form |
| 3511 DCHECK(ra != 0); |
| 3512 set_register(ra, ra_val + offset); |
| 3513 } |
| 3514 break; |
| 3515 } |
| 3516 #endif |
| 3517 |
| 3518 case FAKE_OPCODE: { |
| 3519 if (instr->Bits(MARKER_SUBOPCODE_BIT, MARKER_SUBOPCODE_BIT) == 1) { |
| 3520 int marker_code = instr->Bits(STUB_MARKER_HIGH_BIT, 0); |
| 3521 DCHECK(marker_code < F_NEXT_AVAILABLE_STUB_MARKER); |
| 3522 PrintF("Hit stub-marker: %d (EMIT_STUB_MARKER)\n", marker_code); |
| 3523 } else { |
| 3524 int fake_opcode = instr->Bits(FAKE_OPCODE_HIGH_BIT, 0); |
| 3525 if (fake_opcode == fBKPT) { |
| 3526 PPCDebugger dbg(this); |
| 3527 PrintF("Simulator hit BKPT.\n"); |
| 3528 dbg.Debug(); |
| 3529 } else { |
| 3530 DCHECK(fake_opcode < fLastFaker); |
| 3531 PrintF("Hit ARM opcode: %d(FAKE_OPCODE defined in constant-ppc.h)\n", |
| 3532 fake_opcode); |
| 3533 UNIMPLEMENTED(); |
| 3534 } |
| 3535 } |
| 3536 break; |
| 3537 } |
| 3538 |
| 3539 default: { |
| 3540 UNIMPLEMENTED(); |
| 3541 break; |
| 3542 } |
| 3543 } |
| 3544 } // NOLINT |
| 3545 |
| 3546 |
| 3547 void Simulator::Trace(Instruction* instr) { |
| 3548 disasm::NameConverter converter; |
| 3549 disasm::Disassembler dasm(converter); |
| 3550 // use a reasonably large buffer |
| 3551 v8::internal::EmbeddedVector<char, 256> buffer; |
| 3552 dasm.InstructionDecode(buffer, reinterpret_cast<byte*>(instr)); |
| 3553 PrintF("%05d %08" V8PRIxPTR " %s\n", icount_, |
| 3554 reinterpret_cast<intptr_t>(instr), buffer.start()); |
| 3555 } |
| 3556 |
| 3557 |
| 3558 // Executes the current instruction. |
| 3559 void Simulator::ExecuteInstruction(Instruction* instr) { |
| 3560 if (v8::internal::FLAG_check_icache) { |
| 3561 CheckICache(isolate_->simulator_i_cache(), instr); |
| 3562 } |
| 3563 pc_modified_ = false; |
| 3564 if (::v8::internal::FLAG_trace_sim) { |
| 3565 Trace(instr); |
| 3566 } |
| 3567 int opcode = instr->OpcodeValue() << 26; |
| 3568 if (opcode == TWI) { |
| 3569 SoftwareInterrupt(instr); |
| 3570 } else { |
| 3571 ExecuteGeneric(instr); |
| 3572 } |
| 3573 if (!pc_modified_) { |
| 3574 set_pc(reinterpret_cast<intptr_t>(instr) + Instruction::kInstrSize); |
| 3575 } |
| 3576 } |
| 3577 |
| 3578 |
| 3579 void Simulator::Execute() { |
| 3580 // Get the PC to simulate. Cannot use the accessor here as we need the |
| 3581 // raw PC value and not the one used as input to arithmetic instructions. |
| 3582 intptr_t program_counter = get_pc(); |
| 3583 |
| 3584 if (::v8::internal::FLAG_stop_sim_at == 0) { |
| 3585 // Fast version of the dispatch loop without checking whether the simulator |
| 3586 // should be stopping at a particular executed instruction. |
| 3587 while (program_counter != end_sim_pc) { |
| 3588 Instruction* instr = reinterpret_cast<Instruction*>(program_counter); |
| 3589 icount_++; |
| 3590 ExecuteInstruction(instr); |
| 3591 program_counter = get_pc(); |
| 3592 } |
| 3593 } else { |
| 3594 // FLAG_stop_sim_at is at the non-default value. Stop in the debugger when |
| 3595 // we reach the particular instuction count. |
| 3596 while (program_counter != end_sim_pc) { |
| 3597 Instruction* instr = reinterpret_cast<Instruction*>(program_counter); |
| 3598 icount_++; |
| 3599 if (icount_ == ::v8::internal::FLAG_stop_sim_at) { |
| 3600 PPCDebugger dbg(this); |
| 3601 dbg.Debug(); |
| 3602 } else { |
| 3603 ExecuteInstruction(instr); |
| 3604 } |
| 3605 program_counter = get_pc(); |
| 3606 } |
| 3607 } |
| 3608 } |
| 3609 |
| 3610 |
| 3611 void Simulator::CallInternal(byte* entry) { |
| 3612 // Prepare to execute the code at entry |
| 3613 #if ABI_USES_FUNCTION_DESCRIPTORS |
| 3614 // entry is the function descriptor |
| 3615 set_pc(*(reinterpret_cast<intptr_t*>(entry))); |
| 3616 #else |
| 3617 // entry is the instruction address |
| 3618 set_pc(reinterpret_cast<intptr_t>(entry)); |
| 3619 #endif |
| 3620 |
| 3621 // Put down marker for end of simulation. The simulator will stop simulation |
| 3622 // when the PC reaches this value. By saving the "end simulation" value into |
| 3623 // the LR the simulation stops when returning to this call point. |
| 3624 special_reg_lr_ = end_sim_pc; |
| 3625 |
| 3626 // Remember the values of non-volatile registers. |
| 3627 intptr_t r2_val = get_register(r2); |
| 3628 intptr_t r13_val = get_register(r13); |
| 3629 intptr_t r14_val = get_register(r14); |
| 3630 intptr_t r15_val = get_register(r15); |
| 3631 intptr_t r16_val = get_register(r16); |
| 3632 intptr_t r17_val = get_register(r17); |
| 3633 intptr_t r18_val = get_register(r18); |
| 3634 intptr_t r19_val = get_register(r19); |
| 3635 intptr_t r20_val = get_register(r20); |
| 3636 intptr_t r21_val = get_register(r21); |
| 3637 intptr_t r22_val = get_register(r22); |
| 3638 intptr_t r23_val = get_register(r23); |
| 3639 intptr_t r24_val = get_register(r24); |
| 3640 intptr_t r25_val = get_register(r25); |
| 3641 intptr_t r26_val = get_register(r26); |
| 3642 intptr_t r27_val = get_register(r27); |
| 3643 intptr_t r28_val = get_register(r28); |
| 3644 intptr_t r29_val = get_register(r29); |
| 3645 intptr_t r30_val = get_register(r30); |
| 3646 intptr_t r31_val = get_register(fp); |
| 3647 |
| 3648 // Set up the non-volatile registers with a known value. To be able to check |
| 3649 // that they are preserved properly across JS execution. |
| 3650 intptr_t callee_saved_value = icount_; |
| 3651 set_register(r2, callee_saved_value); |
| 3652 set_register(r13, callee_saved_value); |
| 3653 set_register(r14, callee_saved_value); |
| 3654 set_register(r15, callee_saved_value); |
| 3655 set_register(r16, callee_saved_value); |
| 3656 set_register(r17, callee_saved_value); |
| 3657 set_register(r18, callee_saved_value); |
| 3658 set_register(r19, callee_saved_value); |
| 3659 set_register(r20, callee_saved_value); |
| 3660 set_register(r21, callee_saved_value); |
| 3661 set_register(r22, callee_saved_value); |
| 3662 set_register(r23, callee_saved_value); |
| 3663 set_register(r24, callee_saved_value); |
| 3664 set_register(r25, callee_saved_value); |
| 3665 set_register(r26, callee_saved_value); |
| 3666 set_register(r27, callee_saved_value); |
| 3667 set_register(r28, callee_saved_value); |
| 3668 set_register(r29, callee_saved_value); |
| 3669 set_register(r30, callee_saved_value); |
| 3670 set_register(fp, callee_saved_value); |
| 3671 |
| 3672 // Start the simulation |
| 3673 Execute(); |
| 3674 |
| 3675 // Check that the non-volatile registers have been preserved. |
| 3676 CHECK_EQ(callee_saved_value, get_register(r2)); |
| 3677 CHECK_EQ(callee_saved_value, get_register(r13)); |
| 3678 CHECK_EQ(callee_saved_value, get_register(r14)); |
| 3679 CHECK_EQ(callee_saved_value, get_register(r15)); |
| 3680 CHECK_EQ(callee_saved_value, get_register(r16)); |
| 3681 CHECK_EQ(callee_saved_value, get_register(r17)); |
| 3682 CHECK_EQ(callee_saved_value, get_register(r18)); |
| 3683 CHECK_EQ(callee_saved_value, get_register(r19)); |
| 3684 CHECK_EQ(callee_saved_value, get_register(r20)); |
| 3685 CHECK_EQ(callee_saved_value, get_register(r21)); |
| 3686 CHECK_EQ(callee_saved_value, get_register(r22)); |
| 3687 CHECK_EQ(callee_saved_value, get_register(r23)); |
| 3688 CHECK_EQ(callee_saved_value, get_register(r24)); |
| 3689 CHECK_EQ(callee_saved_value, get_register(r25)); |
| 3690 CHECK_EQ(callee_saved_value, get_register(r26)); |
| 3691 CHECK_EQ(callee_saved_value, get_register(r27)); |
| 3692 CHECK_EQ(callee_saved_value, get_register(r28)); |
| 3693 CHECK_EQ(callee_saved_value, get_register(r29)); |
| 3694 CHECK_EQ(callee_saved_value, get_register(r30)); |
| 3695 CHECK_EQ(callee_saved_value, get_register(fp)); |
| 3696 |
| 3697 // Restore non-volatile registers with the original value. |
| 3698 set_register(r2, r2_val); |
| 3699 set_register(r13, r13_val); |
| 3700 set_register(r14, r14_val); |
| 3701 set_register(r15, r15_val); |
| 3702 set_register(r16, r16_val); |
| 3703 set_register(r17, r17_val); |
| 3704 set_register(r18, r18_val); |
| 3705 set_register(r19, r19_val); |
| 3706 set_register(r20, r20_val); |
| 3707 set_register(r21, r21_val); |
| 3708 set_register(r22, r22_val); |
| 3709 set_register(r23, r23_val); |
| 3710 set_register(r24, r24_val); |
| 3711 set_register(r25, r25_val); |
| 3712 set_register(r26, r26_val); |
| 3713 set_register(r27, r27_val); |
| 3714 set_register(r28, r28_val); |
| 3715 set_register(r29, r29_val); |
| 3716 set_register(r30, r30_val); |
| 3717 set_register(fp, r31_val); |
| 3718 } |
| 3719 |
| 3720 |
| 3721 intptr_t Simulator::Call(byte* entry, int argument_count, ...) { |
| 3722 va_list parameters; |
| 3723 va_start(parameters, argument_count); |
| 3724 // Set up arguments |
| 3725 |
| 3726 // First eight arguments passed in registers r3-r10. |
| 3727 int reg_arg_count = (argument_count > 8) ? 8 : argument_count; |
| 3728 int stack_arg_count = argument_count - reg_arg_count; |
| 3729 for (int i = 0; i < reg_arg_count; i++) { |
| 3730 set_register(i + 3, va_arg(parameters, intptr_t)); |
| 3731 } |
| 3732 |
| 3733 // Remaining arguments passed on stack. |
| 3734 intptr_t original_stack = get_register(sp); |
| 3735 // Compute position of stack on entry to generated code. |
| 3736 intptr_t entry_stack = |
| 3737 (original_stack - |
| 3738 (kNumRequiredStackFrameSlots + stack_arg_count) * sizeof(intptr_t)); |
| 3739 if (base::OS::ActivationFrameAlignment() != 0) { |
| 3740 entry_stack &= -base::OS::ActivationFrameAlignment(); |
| 3741 } |
| 3742 // Store remaining arguments on stack, from low to high memory. |
| 3743 // +2 is a hack for the LR slot + old SP on PPC |
| 3744 intptr_t* stack_argument = |
| 3745 reinterpret_cast<intptr_t*>(entry_stack) + kStackFrameExtraParamSlot; |
| 3746 for (int i = 0; i < stack_arg_count; i++) { |
| 3747 stack_argument[i] = va_arg(parameters, intptr_t); |
| 3748 } |
| 3749 va_end(parameters); |
| 3750 set_register(sp, entry_stack); |
| 3751 |
| 3752 CallInternal(entry); |
| 3753 |
| 3754 // Pop stack passed arguments. |
| 3755 CHECK_EQ(entry_stack, get_register(sp)); |
| 3756 set_register(sp, original_stack); |
| 3757 |
| 3758 intptr_t result = get_register(r3); |
| 3759 return result; |
| 3760 } |
| 3761 |
| 3762 |
| 3763 void Simulator::CallFP(byte* entry, double d0, double d1) { |
| 3764 set_d_register_from_double(1, d0); |
| 3765 set_d_register_from_double(2, d1); |
| 3766 CallInternal(entry); |
| 3767 } |
| 3768 |
| 3769 |
| 3770 int32_t Simulator::CallFPReturnsInt(byte* entry, double d0, double d1) { |
| 3771 CallFP(entry, d0, d1); |
| 3772 int32_t result = get_register(r3); |
| 3773 return result; |
| 3774 } |
| 3775 |
| 3776 |
| 3777 double Simulator::CallFPReturnsDouble(byte* entry, double d0, double d1) { |
| 3778 CallFP(entry, d0, d1); |
| 3779 return get_double_from_d_register(1); |
| 3780 } |
| 3781 |
| 3782 |
| 3783 uintptr_t Simulator::PushAddress(uintptr_t address) { |
| 3784 uintptr_t new_sp = get_register(sp) - sizeof(uintptr_t); |
| 3785 uintptr_t* stack_slot = reinterpret_cast<uintptr_t*>(new_sp); |
| 3786 *stack_slot = address; |
| 3787 set_register(sp, new_sp); |
| 3788 return new_sp; |
| 3789 } |
| 3790 |
| 3791 |
| 3792 uintptr_t Simulator::PopAddress() { |
| 3793 uintptr_t current_sp = get_register(sp); |
| 3794 uintptr_t* stack_slot = reinterpret_cast<uintptr_t*>(current_sp); |
| 3795 uintptr_t address = *stack_slot; |
| 3796 set_register(sp, current_sp + sizeof(uintptr_t)); |
| 3797 return address; |
| 3798 } |
| 3799 } |
| 3800 } // namespace v8::internal |
| 3801 |
| 3802 #endif // USE_SIMULATOR |
| 3803 #endif // V8_TARGET_ARCH_PPC |
OLD | NEW |