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1 ; Tests insertelement and extractelement vector instructions. | 1 ; Tests insertelement and extractelement vector instructions. |
2 | 2 |
3 | 3 |
4 ; RUN: llvm-as < %s | pnacl-freeze \ | 4 ; RUN: llvm-as < %s | pnacl-freeze -allow-local-symbol-tables \ |
5 ; RUN: | %llvm2ice -notranslate -verbose=inst -build-on-read \ | 5 ; RUN: | %llvm2ice -notranslate -verbose=inst -build-on-read \ |
6 ; RUN: -allow-pnacl-reader-error-recovery \ | 6 ; RUN: -allow-pnacl-reader-error-recovery \ |
| 7 ; RUN: -allow-local-symbol-tables \ |
7 ; RUN: | FileCheck %s | 8 ; RUN: | FileCheck %s |
8 | 9 |
9 ; TODO(kschimpf): Change index arguments to valid constant indices once | 10 ; TODO(kschimpf): Change index arguments to valid constant indices once |
10 ; we can handle constants. | 11 ; we can handle constants. |
11 | 12 |
12 define void @ExtractV4xi1(<4 x i1> %v, i32 %i) { | 13 define void @ExtractV4xi1(<4 x i1> %v, i32 %i) { |
| 14 entry: |
13 %e = extractelement <4 x i1> %v, i32 %i | 15 %e = extractelement <4 x i1> %v, i32 %i |
14 ret void | 16 ret void |
15 } | 17 } |
16 | 18 |
17 ; CHECK: define void @ExtractV4xi1(<4 x i1> %__0, i32 %__1) { | 19 ; CHECK: define void @ExtractV4xi1(<4 x i1> %v, i32 %i) { |
18 ; CHECK-NEXT: __0: | 20 ; CHECK-NEXT: entry: |
19 ; CHECK-NEXT: %__2 = extractelement <4 x i1> %__0, i32 %__1 | 21 ; CHECK-NEXT: %e = extractelement <4 x i1> %v, i32 %i |
20 ; CHECK-NEXT: ret void | 22 ; CHECK-NEXT: ret void |
21 ; CHECK-NEXT: } | 23 ; CHECK-NEXT: } |
22 | 24 |
23 define void @ExtractV8xi1(<8 x i1> %v, i32 %i) { | 25 define void @ExtractV8xi1(<8 x i1> %v, i32 %i) { |
| 26 entry: |
24 %e = extractelement <8 x i1> %v, i32 %i | 27 %e = extractelement <8 x i1> %v, i32 %i |
25 ret void | 28 ret void |
26 } | 29 } |
27 | 30 |
28 ; CHECK-NEXT: define void @ExtractV8xi1(<8 x i1> %__0, i32 %__1) { | 31 ; CHECK-NEXT: define void @ExtractV8xi1(<8 x i1> %v, i32 %i) { |
29 ; CHECK-NEXT: __0: | 32 ; CHECK-NEXT: entry: |
30 ; CHECK-NEXT: %__2 = extractelement <8 x i1> %__0, i32 %__1 | 33 ; CHECK-NEXT: %e = extractelement <8 x i1> %v, i32 %i |
31 ; CHECK-NEXT: ret void | 34 ; CHECK-NEXT: ret void |
32 ; CHECK-NEXT: } | 35 ; CHECK-NEXT: } |
33 | 36 |
34 define void @ExtractV16xi1(<16 x i1> %v, i32 %i) { | 37 define void @ExtractV16xi1(<16 x i1> %v, i32 %i) { |
| 38 entry: |
35 %e = extractelement <16 x i1> %v, i32 %i | 39 %e = extractelement <16 x i1> %v, i32 %i |
36 ret void | 40 ret void |
37 } | 41 } |
38 | 42 |
39 ; CHECK-NEXT: define void @ExtractV16xi1(<16 x i1> %__0, i32 %__1) { | 43 ; CHECK-NEXT: define void @ExtractV16xi1(<16 x i1> %v, i32 %i) { |
40 ; CHECK-NEXT: __0: | 44 ; CHECK-NEXT: entry: |
41 ; CHECK-NEXT: %__2 = extractelement <16 x i1> %__0, i32 %__1 | 45 ; CHECK-NEXT: %e = extractelement <16 x i1> %v, i32 %i |
42 ; CHECK-NEXT: ret void | 46 ; CHECK-NEXT: ret void |
43 ; CHECK-NEXT: } | 47 ; CHECK-NEXT: } |
44 | 48 |
45 define void @ExtractV16xi8(<16 x i8> %v, i32 %i) { | 49 define void @ExtractV16xi8(<16 x i8> %v, i32 %i) { |
| 50 entry: |
46 %e = extractelement <16 x i8> %v, i32 %i | 51 %e = extractelement <16 x i8> %v, i32 %i |
47 ret void | 52 ret void |
48 } | 53 } |
49 | 54 |
50 ; CHECK-NEXT: define void @ExtractV16xi8(<16 x i8> %__0, i32 %__1) { | 55 ; CHECK-NEXT: define void @ExtractV16xi8(<16 x i8> %v, i32 %i) { |
51 ; CHECK-NEXT: __0: | 56 ; CHECK-NEXT: entry: |
52 ; CHECK-NEXT: %__2 = extractelement <16 x i8> %__0, i32 %__1 | 57 ; CHECK-NEXT: %e = extractelement <16 x i8> %v, i32 %i |
53 ; CHECK-NEXT: ret void | 58 ; CHECK-NEXT: ret void |
54 ; CHECK-NEXT: } | 59 ; CHECK-NEXT: } |
55 | 60 |
56 define void @ExtractV8xi16(<8 x i16> %v, i32 %i) { | 61 define void @ExtractV8xi16(<8 x i16> %v, i32 %i) { |
| 62 entry: |
57 %e = extractelement <8 x i16> %v, i32 %i | 63 %e = extractelement <8 x i16> %v, i32 %i |
58 ret void | 64 ret void |
59 } | 65 } |
60 | 66 |
61 ; CHECK-NEXT: define void @ExtractV8xi16(<8 x i16> %__0, i32 %__1) { | 67 ; CHECK-NEXT: define void @ExtractV8xi16(<8 x i16> %v, i32 %i) { |
62 ; CHECK-NEXT: __0: | 68 ; CHECK-NEXT: entry: |
63 ; CHECK-NEXT: %__2 = extractelement <8 x i16> %__0, i32 %__1 | 69 ; CHECK-NEXT: %e = extractelement <8 x i16> %v, i32 %i |
64 ; CHECK-NEXT: ret void | 70 ; CHECK-NEXT: ret void |
65 ; CHECK-NEXT: } | 71 ; CHECK-NEXT: } |
66 | 72 |
67 define i32 @ExtractV4xi32(<4 x i32> %v, i32 %i) { | 73 define i32 @ExtractV4xi32(<4 x i32> %v, i32 %i) { |
| 74 entry: |
68 %e = extractelement <4 x i32> %v, i32 %i | 75 %e = extractelement <4 x i32> %v, i32 %i |
69 ret i32 %e | 76 ret i32 %e |
70 } | 77 } |
71 | 78 |
72 ; CHECK-NEXT: define i32 @ExtractV4xi32(<4 x i32> %__0, i32 %__1) { | 79 ; CHECK-NEXT: define i32 @ExtractV4xi32(<4 x i32> %v, i32 %i) { |
73 ; CHECK-NEXT: __0: | 80 ; CHECK-NEXT: entry: |
74 ; CHECK-NEXT: %__2 = extractelement <4 x i32> %__0, i32 %__1 | 81 ; CHECK-NEXT: %e = extractelement <4 x i32> %v, i32 %i |
75 ; CHECK-NEXT: ret i32 %__2 | 82 ; CHECK-NEXT: ret i32 %e |
76 ; CHECK-NEXT: } | 83 ; CHECK-NEXT: } |
77 | 84 |
78 define float @ExtractV4xfloat(<4 x float> %v, i32 %i) { | 85 define float @ExtractV4xfloat(<4 x float> %v, i32 %i) { |
| 86 entry: |
79 %e = extractelement <4 x float> %v, i32 %i | 87 %e = extractelement <4 x float> %v, i32 %i |
80 ret float %e | 88 ret float %e |
81 } | 89 } |
82 | 90 |
83 ; CHECK-NEXT: define float @ExtractV4xfloat(<4 x float> %__0, i32 %__1) { | 91 ; CHECK-NEXT: define float @ExtractV4xfloat(<4 x float> %v, i32 %i) { |
84 ; CHECK-NEXT: __0: | 92 ; CHECK-NEXT: entry: |
85 ; CHECK-NEXT: %__2 = extractelement <4 x float> %__0, i32 %__1 | 93 ; CHECK-NEXT: %e = extractelement <4 x float> %v, i32 %i |
86 ; CHECK-NEXT: ret float %__2 | 94 ; CHECK-NEXT: ret float %e |
87 ; CHECK-NEXT: } | 95 ; CHECK-NEXT: } |
88 | 96 |
89 define <4 x i1> @InsertV4xi1(<4 x i1> %v, i32 %pe, i32 %i) { | 97 define <4 x i1> @InsertV4xi1(<4 x i1> %v, i32 %pe, i32 %i) { |
| 98 entry: |
90 %e = trunc i32 %pe to i1 | 99 %e = trunc i32 %pe to i1 |
91 %r = insertelement <4 x i1> %v, i1 %e, i32 %i | 100 %r = insertelement <4 x i1> %v, i1 %e, i32 %i |
92 ret <4 x i1> %r | 101 ret <4 x i1> %r |
93 } | 102 } |
94 | 103 |
95 ; CHECK-NEXT: define <4 x i1> @InsertV4xi1(<4 x i1> %__0, i32 %__1, i32 %__2) { | 104 ; CHECK-NEXT: define <4 x i1> @InsertV4xi1(<4 x i1> %v, i32 %pe, i32 %i) { |
96 ; CHECK-NEXT: __0: | 105 ; CHECK-NEXT: entry: |
97 ; CHECK-NEXT: %__3 = trunc i32 %__1 to i1 | 106 ; CHECK-NEXT: %e = trunc i32 %pe to i1 |
98 ; CHECK-NEXT: %__4 = insertelement <4 x i1> %__0, i1 %__3, i32 %__2 | 107 ; CHECK-NEXT: %r = insertelement <4 x i1> %v, i1 %e, i32 %i |
99 ; CHECK-NEXT: ret i1 %__4 | 108 ; CHECK-NEXT: ret i1 %r |
100 ; CHECK-NEXT: } | 109 ; CHECK-NEXT: } |
101 | 110 |
102 define <8 x i1> @InsertV8xi1(<8 x i1> %v, i32 %pe, i32 %i) { | 111 define <8 x i1> @InsertV8xi1(<8 x i1> %v, i32 %pe, i32 %i) { |
| 112 entry: |
103 %e = trunc i32 %pe to i1 | 113 %e = trunc i32 %pe to i1 |
104 %r = insertelement <8 x i1> %v, i1 %e, i32 %i | 114 %r = insertelement <8 x i1> %v, i1 %e, i32 %i |
105 ret <8 x i1> %r | 115 ret <8 x i1> %r |
106 } | 116 } |
107 | 117 |
108 ; CHECK-NEXT: define <8 x i1> @InsertV8xi1(<8 x i1> %__0, i32 %__1, i32 %__2) { | 118 ; CHECK-NEXT: define <8 x i1> @InsertV8xi1(<8 x i1> %v, i32 %pe, i32 %i) { |
109 ; CHECK-NEXT: __0: | 119 ; CHECK-NEXT: entry: |
110 ; CHECK-NEXT: %__3 = trunc i32 %__1 to i1 | 120 ; CHECK-NEXT: %e = trunc i32 %pe to i1 |
111 ; CHECK-NEXT: %__4 = insertelement <8 x i1> %__0, i1 %__3, i32 %__2 | 121 ; CHECK-NEXT: %r = insertelement <8 x i1> %v, i1 %e, i32 %i |
112 ; CHECK-NEXT: ret i1 %__4 | 122 ; CHECK-NEXT: ret i1 %r |
113 ; CHECK-NEXT: } | 123 ; CHECK-NEXT: } |
114 | 124 |
115 define <16 x i1> @InsertV16xi1(<16 x i1> %v, i32 %pe, i32 %i) { | 125 define <16 x i1> @InsertV16xi1(<16 x i1> %v, i32 %pe, i32 %i) { |
| 126 entry: |
116 %e = trunc i32 %pe to i1 | 127 %e = trunc i32 %pe to i1 |
117 %r = insertelement <16 x i1> %v, i1 %e, i32 %i | 128 %r = insertelement <16 x i1> %v, i1 %e, i32 %i |
118 ret <16 x i1> %r | 129 ret <16 x i1> %r |
119 } | 130 } |
120 | 131 |
121 ; CHECK-NEXT: define <16 x i1> @InsertV16xi1(<16 x i1> %__0, i32 %__1, i32 %__2)
{ | 132 ; CHECK-NEXT: define <16 x i1> @InsertV16xi1(<16 x i1> %v, i32 %pe, i32 %i) { |
122 ; CHECK-NEXT: __0: | 133 ; CHECK-NEXT: entry: |
123 ; CHECK-NEXT: %__3 = trunc i32 %__1 to i1 | 134 ; CHECK-NEXT: %e = trunc i32 %pe to i1 |
124 ; CHECK-NEXT: %__4 = insertelement <16 x i1> %__0, i1 %__3, i32 %__2 | 135 ; CHECK-NEXT: %r = insertelement <16 x i1> %v, i1 %e, i32 %i |
125 ; CHECK-NEXT: ret i1 %__4 | 136 ; CHECK-NEXT: ret i1 %r |
126 ; CHECK-NEXT: } | 137 ; CHECK-NEXT: } |
127 | 138 |
128 define <16 x i8> @InsertV16xi8(<16 x i8> %v, i32 %pe, i32 %i) { | 139 define <16 x i8> @InsertV16xi8(<16 x i8> %v, i32 %pe, i32 %i) { |
| 140 entry: |
129 %e = trunc i32 %pe to i8 | 141 %e = trunc i32 %pe to i8 |
130 %r = insertelement <16 x i8> %v, i8 %e, i32 %i | 142 %r = insertelement <16 x i8> %v, i8 %e, i32 %i |
131 ret <16 x i8> %r | 143 ret <16 x i8> %r |
132 } | 144 } |
133 | 145 |
134 ; CHECK-NEXT: define <16 x i8> @InsertV16xi8(<16 x i8> %__0, i32 %__1, i32 %__2)
{ | 146 ; CHECK-NEXT: define <16 x i8> @InsertV16xi8(<16 x i8> %v, i32 %pe, i32 %i) { |
135 ; CHECK-NEXT: __0: | 147 ; CHECK-NEXT: entry: |
136 ; CHECK-NEXT: %__3 = trunc i32 %__1 to i8 | 148 ; CHECK-NEXT: %e = trunc i32 %pe to i8 |
137 ; CHECK-NEXT: %__4 = insertelement <16 x i8> %__0, i8 %__3, i32 %__2 | 149 ; CHECK-NEXT: %r = insertelement <16 x i8> %v, i8 %e, i32 %i |
138 ; CHECK-NEXT: ret i8 %__4 | 150 ; CHECK-NEXT: ret i8 %r |
139 ; CHECK-NEXT: } | 151 ; CHECK-NEXT: } |
140 | 152 |
141 define <8 x i16> @InsertV8xi16(<8 x i16> %v, i32 %pe, i32 %i) { | 153 define <8 x i16> @InsertV8xi16(<8 x i16> %v, i32 %pe, i32 %i) { |
| 154 entry: |
142 %e = trunc i32 %pe to i16 | 155 %e = trunc i32 %pe to i16 |
143 %r = insertelement <8 x i16> %v, i16 %e, i32 %i | 156 %r = insertelement <8 x i16> %v, i16 %e, i32 %i |
144 ret <8 x i16> %r | 157 ret <8 x i16> %r |
145 } | 158 } |
146 | 159 |
147 ; CHECK-NEXT: define <8 x i16> @InsertV8xi16(<8 x i16> %__0, i32 %__1, i32 %__2)
{ | 160 ; CHECK-NEXT: define <8 x i16> @InsertV8xi16(<8 x i16> %v, i32 %pe, i32 %i) { |
148 ; CHECK-NEXT: __0: | 161 ; CHECK-NEXT: entry: |
149 ; CHECK-NEXT: %__3 = trunc i32 %__1 to i16 | 162 ; CHECK-NEXT: %e = trunc i32 %pe to i16 |
150 ; CHECK-NEXT: %__4 = insertelement <8 x i16> %__0, i16 %__3, i32 %__2 | 163 ; CHECK-NEXT: %r = insertelement <8 x i16> %v, i16 %e, i32 %i |
151 ; CHECK-NEXT: ret i16 %__4 | 164 ; CHECK-NEXT: ret i16 %r |
152 ; CHECK-NEXT: } | 165 ; CHECK-NEXT: } |
153 | 166 |
154 define <4 x i32> @InsertV16xi32(<4 x i32> %v, i32 %e, i32 %i) { | 167 define <4 x i32> @InsertV4xi32(<4 x i32> %v, i32 %e, i32 %i) { |
| 168 entry: |
155 %r = insertelement <4 x i32> %v, i32 %e, i32 %i | 169 %r = insertelement <4 x i32> %v, i32 %e, i32 %i |
156 ret <4 x i32> %r | 170 ret <4 x i32> %r |
157 } | 171 } |
158 | 172 |
159 ; CHECK-NEXT: define <4 x i32> @InsertV16xi32(<4 x i32> %__0, i32 %__1, i32 %__2
) { | 173 ; CHECK-NEXT: define <4 x i32> @InsertV4xi32(<4 x i32> %v, i32 %e, i32 %i) { |
160 ; CHECK-NEXT: __0: | 174 ; CHECK-NEXT: entry: |
161 ; CHECK-NEXT: %__3 = insertelement <4 x i32> %__0, i32 %__1, i32 %__2 | 175 ; CHECK-NEXT: %r = insertelement <4 x i32> %v, i32 %e, i32 %i |
162 ; CHECK-NEXT: ret i32 %__3 | 176 ; CHECK-NEXT: ret i32 %r |
163 ; CHECK-NEXT: } | 177 ; CHECK-NEXT: } |
164 | 178 |
165 define <4 x float> @InsertV16xfloat(<4 x float> %v, float %e, i32 %i) { | 179 define <4 x float> @InsertV4xfloat(<4 x float> %v, float %e, i32 %i) { |
| 180 entry: |
166 %r = insertelement <4 x float> %v, float %e, i32 %i | 181 %r = insertelement <4 x float> %v, float %e, i32 %i |
167 ret <4 x float> %r | 182 ret <4 x float> %r |
168 } | 183 } |
169 | 184 |
170 ; CHECK-NEXT: define <4 x float> @InsertV16xfloat(<4 x float> %__0, float %__1,
i32 %__2) { | 185 ; CHECK-NEXT: define <4 x float> @InsertV4xfloat(<4 x float> %v, float %e, i32 %
i) { |
171 ; CHECK-NEXT: __0: | 186 ; CHECK-NEXT: entry: |
172 ; CHECK-NEXT: %__3 = insertelement <4 x float> %__0, float %__1, i32 %__2 | 187 ; CHECK-NEXT: %r = insertelement <4 x float> %v, float %e, i32 %i |
173 ; CHECK-NEXT: ret float %__3 | 188 ; CHECK-NEXT: ret float %r |
174 ; CHECK-NEXT: } | 189 ; CHECK-NEXT: } |
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