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Issue 559123003: Fix awesomeness in X64 assembler. (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: Created 6 years, 3 months ago
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1 // Copyright 2012 the V8 project authors. All rights reserved. 1 // Copyright 2012 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #include "src/v8.h" 5 #include "src/v8.h"
6 6
7 #if V8_TARGET_ARCH_X64 7 #if V8_TARGET_ARCH_X64
8 8
9 #include "src/base/bits.h" 9 #include "src/base/bits.h"
10 #include "src/macro-assembler.h" 10 #include "src/macro-assembler.h"
(...skipping 1159 matching lines...) Expand 10 before | Expand all | Expand 10 after
1170 emit_optional_rex_32(dst, src); 1170 emit_optional_rex_32(dst, src);
1171 } 1171 }
1172 emit(0x8A); 1172 emit(0x8A);
1173 emit_operand(dst, src); 1173 emit_operand(dst, src);
1174 } 1174 }
1175 1175
1176 1176
1177 void Assembler::movb(Register dst, Immediate imm) { 1177 void Assembler::movb(Register dst, Immediate imm) {
1178 EnsureSpace ensure_space(this); 1178 EnsureSpace ensure_space(this);
1179 if (!dst.is_byte_register()) { 1179 if (!dst.is_byte_register()) {
1180 // Register is not one of al, bl, cl, dl. Its encoding needs REX.
1180 emit_rex_32(dst); 1181 emit_rex_32(dst);
1181 } 1182 }
1182 emit(0xB0 + dst.low_bits()); 1183 emit(0xB0 + dst.low_bits());
1183 emit(imm.value_); 1184 emit(imm.value_);
1184 } 1185 }
1185 1186
1186 1187
1187 void Assembler::movb(const Operand& dst, Register src) { 1188 void Assembler::movb(const Operand& dst, Register src) {
1188 EnsureSpace ensure_space(this); 1189 EnsureSpace ensure_space(this);
1189 if (!src.is_byte_register()) { 1190 if (!src.is_byte_register()) {
1191 // Register is not one of al, bl, cl, dl. Its encoding needs REX.
1190 emit_rex_32(src, dst); 1192 emit_rex_32(src, dst);
1191 } else { 1193 } else {
1192 emit_optional_rex_32(src, dst); 1194 emit_optional_rex_32(src, dst);
1193 } 1195 }
1194 emit(0x88); 1196 emit(0x88);
1195 emit_operand(src, dst); 1197 emit_operand(src, dst);
1196 } 1198 }
1197 1199
1198 1200
1199 void Assembler::movb(const Operand& dst, Immediate imm) { 1201 void Assembler::movb(const Operand& dst, Immediate imm) {
(...skipping 191 matching lines...) Expand 10 before | Expand all | Expand 10 after
1391 emit(0x0F); 1393 emit(0x0F);
1392 emit(0xB6); 1394 emit(0xB6);
1393 emit_operand(dst, src); 1395 emit_operand(dst, src);
1394 } 1396 }
1395 1397
1396 1398
1397 void Assembler::emit_movzxb(Register dst, Register src, int size) { 1399 void Assembler::emit_movzxb(Register dst, Register src, int size) {
1398 EnsureSpace ensure_space(this); 1400 EnsureSpace ensure_space(this);
1399 // 32 bit operations zero the top 32 bits of 64 bit registers. Therefore 1401 // 32 bit operations zero the top 32 bits of 64 bit registers. Therefore
1400 // there is no need to make this a 64 bit operation. 1402 // there is no need to make this a 64 bit operation.
1401 emit_optional_rex_32(dst, src); 1403 if (!src.is_byte_register()) {
1404 // Register is not one of al, bl, cl, dl. Its encoding needs REX.
1405 emit_rex_32(dst, src);
1406 } else {
1407 emit_optional_rex_32(dst, src);
1408 }
1402 emit(0x0F); 1409 emit(0x0F);
1403 emit(0xB6); 1410 emit(0xB6);
1404 emit_modrm(dst, src); 1411 emit_modrm(dst, src);
1405 } 1412 }
1406 1413
1407 1414
1408 void Assembler::emit_movzxw(Register dst, const Operand& src, int size) { 1415 void Assembler::emit_movzxw(Register dst, const Operand& src, int size) {
1409 EnsureSpace ensure_space(this); 1416 EnsureSpace ensure_space(this);
1410 // 32 bit operations zero the top 32 bits of 64 bit registers. Therefore 1417 // 32 bit operations zero the top 32 bits of 64 bit registers. Therefore
1411 // there is no need to make this a 64 bit operation. 1418 // there is no need to make this a 64 bit operation.
(...skipping 235 matching lines...) Expand 10 before | Expand all | Expand 10 after
1647 } 1654 }
1648 1655
1649 1656
1650 void Assembler::setcc(Condition cc, Register reg) { 1657 void Assembler::setcc(Condition cc, Register reg) {
1651 if (cc > last_condition) { 1658 if (cc > last_condition) {
1652 movb(reg, Immediate(cc == always ? 1 : 0)); 1659 movb(reg, Immediate(cc == always ? 1 : 0));
1653 return; 1660 return;
1654 } 1661 }
1655 EnsureSpace ensure_space(this); 1662 EnsureSpace ensure_space(this);
1656 DCHECK(is_uint4(cc)); 1663 DCHECK(is_uint4(cc));
1657 if (!reg.is_byte_register()) { // Use x64 byte registers, where different. 1664 if (!reg.is_byte_register()) {
1665 // Register is not one of al, bl, cl, dl. Its encoding needs REX.
1658 emit_rex_32(reg); 1666 emit_rex_32(reg);
1659 } 1667 }
1660 emit(0x0F); 1668 emit(0x0F);
1661 emit(0x90 | cc); 1669 emit(0x90 | cc);
1662 emit_modrm(0x0, reg); 1670 emit_modrm(0x0, reg);
1663 } 1671 }
1664 1672
1665 1673
1666 void Assembler::shld(Register dst, Register src) { 1674 void Assembler::shld(Register dst, Register src) {
1667 EnsureSpace ensure_space(this); 1675 EnsureSpace ensure_space(this);
(...skipping 1319 matching lines...) Expand 10 before | Expand all | Expand 10 after
2987 2995
2988 2996
2989 bool RelocInfo::IsInConstantPool() { 2997 bool RelocInfo::IsInConstantPool() {
2990 return false; 2998 return false;
2991 } 2999 }
2992 3000
2993 3001
2994 } } // namespace v8::internal 3002 } } // namespace v8::internal
2995 3003
2996 #endif // V8_TARGET_ARCH_X64 3004 #endif // V8_TARGET_ARCH_X64
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