ARM64: Change some incorect uses of ptrdiff_t to int64_t.

src/arm64/assembler-arm64.h

 // Copyright 2013 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #ifndef V8_ARM64_ASSEMBLER_ARM64_H_
 #define V8_ARM64_ASSEMBLER_ARM64_H_
 
 #include <list>
 #include <map>
 #include <vector>
@@ skipping 681 matching lines @@
   Extend extend_;
   unsigned shift_amount_;
 };
 
 
 // MemOperand represents a memory operand in a load or store instruction.
 class MemOperand {
  public:
   inline MemOperand();
   inline explicit MemOperand(Register base,
-                             ptrdiff_t offset = 0,
+                             int64_t offset = 0,
                              AddrMode addrmode = Offset);
   inline explicit MemOperand(Register base,
                              Register regoffset,
                              Shift shift = LSL,
                              unsigned shift_amount = 0);
   inline explicit MemOperand(Register base,
                              Register regoffset,
                              Extend extend,
                              unsigned shift_amount = 0);
   inline explicit MemOperand(Register base,
                              const Operand& offset,
                              AddrMode addrmode = Offset);
 
   const Register& base() const { return base_; }
   const Register& regoffset() const { return regoffset_; }
-  ptrdiff_t offset() const { return offset_; }
+  int64_t offset() const { return offset_; }
   AddrMode addrmode() const { return addrmode_; }
   Shift shift() const { return shift_; }
   Extend extend() const { return extend_; }
   unsigned shift_amount() const { return shift_amount_; }
   inline bool IsImmediateOffset() const;
   inline bool IsRegisterOffset() const;
   inline bool IsPreIndex() const;
   inline bool IsPostIndex() const;
 
   // For offset modes, return the offset as an Operand. This helper cannot
   // handle indexed modes.
   inline Operand OffsetAsOperand() const;
 
   enum PairResult {
     kNotPair,   // Can't use a pair instruction.
     kPairAB,    // Can use a pair instruction (operandA has lower address).
     kPairBA     // Can use a pair instruction (operandB has lower address).
   };
   // Check if two MemOperand are consistent for stp/ldp use.
   static PairResult AreConsistentForPair(const MemOperand& operandA,
                                          const MemOperand& operandB,
                                          int access_size_log2 = kXRegSizeLog2);
 
  private:
   Register base_;
   Register regoffset_;
-  ptrdiff_t offset_;
+  int64_t offset_;
   AddrMode addrmode_;
   Shift shift_;
   Extend extend_;
   unsigned shift_amount_;
 };
 
 
 class ConstPool {
  public:
   explicit ConstPool(Assembler* assm)
@@ skipping 1170 matching lines @@
 
     DISALLOW_IMPLICIT_CONSTRUCTORS(BlockPoolsScope);
   };
 
  protected:
   inline const Register& AppropriateZeroRegFor(const CPURegister& reg) const;
 
   void LoadStore(const CPURegister& rt,
                  const MemOperand& addr,
                  LoadStoreOp op);
-  static bool IsImmLSUnscaled(ptrdiff_t offset);
-  static bool IsImmLSScaled(ptrdiff_t offset, LSDataSize size);
+  static bool IsImmLSUnscaled(int64_t offset);
+  static bool IsImmLSScaled(int64_t offset, LSDataSize size);
 
   void LoadStorePair(const CPURegister& rt, const CPURegister& rt2,
                      const MemOperand& addr, LoadStorePairOp op);
-  static bool IsImmLSPair(ptrdiff_t offset, LSDataSize size);
+  static bool IsImmLSPair(int64_t offset, LSDataSize size);
 
   void Logical(const Register& rd,
                const Register& rn,
                const Operand& operand,
                LogicalOp op);
   void LogicalImmediate(const Register& rd,
                         const Register& rn,
                         unsigned n,
                         unsigned imm_s,
                         unsigned imm_r,
@@ skipping 324 matching lines @@
     // Verify no relocation information has been emitted.
     DCHECK(IsConstPoolEmpty());
     // Flush the Instruction cache.
     size_t length = buffer_size_ - kGap;
     CpuFeatures::FlushICache(buffer_, length);
   }
 
   // See definition of PatchAdrFar() for details.
   static const int kAdrFarPatchableNNops = 2;
   static const int kAdrFarPatchableNInstrs = kAdrFarPatchableNNops + 2;
-  void PatchAdrFar(ptrdiff_t target_offset);
+  void PatchAdrFar(int64_t target_offset);
 };
 
 
 class EnsureSpace BASE_EMBEDDED {
  public:
   explicit EnsureSpace(Assembler* assembler) {
     assembler->CheckBufferSpace();
   }
 };
 
 } }  // namespace v8::internal
 
 #endif  // V8_ARM64_ASSEMBLER_ARM64_H_