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Issue 558163006: MIPS64: Fix move operations from coprocessor in simulator. (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: Created 6 years, 3 months ago
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1 // Copyright 2011 the V8 project authors. All rights reserved. 1 // Copyright 2011 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #include <limits.h> 5 #include <limits.h>
6 #include <stdarg.h> 6 #include <stdarg.h>
7 #include <stdlib.h> 7 #include <stdlib.h>
8 #include <cmath> 8 #include <cmath>
9 9
10 #include "src/v8.h" 10 #include "src/v8.h"
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1102 return static_cast<int32_t>(FPUregisters_[fpureg] & 0xffffffff); 1102 return static_cast<int32_t>(FPUregisters_[fpureg] & 0xffffffff);
1103 } 1103 }
1104 1104
1105 1105
1106 int32_t Simulator::get_fpu_register_signed_word(int fpureg) const { 1106 int32_t Simulator::get_fpu_register_signed_word(int fpureg) const {
1107 DCHECK((fpureg >= 0) && (fpureg < kNumFPURegisters)); 1107 DCHECK((fpureg >= 0) && (fpureg < kNumFPURegisters));
1108 return static_cast<int32_t>(FPUregisters_[fpureg] & 0xffffffff); 1108 return static_cast<int32_t>(FPUregisters_[fpureg] & 0xffffffff);
1109 } 1109 }
1110 1110
1111 1111
1112 uint32_t Simulator::get_fpu_register_hi_word(int fpureg) const { 1112 int32_t Simulator::get_fpu_register_hi_word(int fpureg) const {
1113 DCHECK((fpureg >= 0) && (fpureg < kNumFPURegisters)); 1113 DCHECK((fpureg >= 0) && (fpureg < kNumFPURegisters));
1114 return static_cast<uint32_t>((FPUregisters_[fpureg] >> 32) & 0xffffffff); 1114 return static_cast<int32_t>((FPUregisters_[fpureg] >> 32) & 0xffffffff);
1115 } 1115 }
1116 1116
1117 1117
1118 float Simulator::get_fpu_register_float(int fpureg) const { 1118 float Simulator::get_fpu_register_float(int fpureg) const {
1119 DCHECK((fpureg >= 0) && (fpureg < kNumFPURegisters)); 1119 DCHECK((fpureg >= 0) && (fpureg < kNumFPURegisters));
1120 return *bit_cast<float*>(const_cast<int64_t*>(&FPUregisters_[fpureg])); 1120 return *bit_cast<float*>(const_cast<int64_t*>(&FPUregisters_[fpureg]));
1121 } 1121 }
1122 1122
1123 1123
1124 double Simulator::get_fpu_register_double(int fpureg) const { 1124 double Simulator::get_fpu_register_double(int fpureg) const {
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3437 } 3437 }
3438 3438
3439 3439
3440 #undef UNSUPPORTED 3440 #undef UNSUPPORTED
3441 3441
3442 } } // namespace v8::internal 3442 } } // namespace v8::internal
3443 3443
3444 #endif // USE_SIMULATOR 3444 #endif // USE_SIMULATOR
3445 3445
3446 #endif // V8_TARGET_ARCH_MIPS64 3446 #endif // V8_TARGET_ARCH_MIPS64
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