Subzero: Fix incorrect address mode inference involving Phi temporaries.

src/IceOperand.h

 //===- subzero/src/IceOperand.h - High-level operands -----------*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file declares the Operand class and its target-independent
@@ skipping 331 matching lines @@
   }
 
   Inst *getDefinition() const { return DefInst; }
   void setDefinition(Inst *Inst, const CfgNode *Node);
   void replaceDefinition(Inst *Inst, const CfgNode *Node);
 
   const CfgNode *getLocalUseNode() const { return DefNode; }
   bool isMultiblockLife() const { return (DefNode == NULL); }
   void setUse(const Inst *Inst, const CfgNode *Node);
 
+  // Multidef means a variable is non-SSA and has multiple defining
+  // instructions.  Currently this classification is limited to SSA
+  // lowering temporaries where the definitions are in different basic
+  // blocks, and it is not maintained during target lowering when the
+  // same temporary may be updated in consecutive instructions.
+  bool getIsMultidef() const { return IsMultidef; }
+  void setIsMultidef() { IsMultidef = true; }
+
   bool getIsArg() const { return IsArgument; }
   void setIsArg(Cfg *Func, bool IsArg = true);
 
   int32_t getStackOffset() const { return StackOffset; }
   void setStackOffset(int32_t Offset) { StackOffset = Offset; }
 
   static const int32_t NoRegister = -1;
   bool hasReg() const { return getRegNum() != NoRegister; }
   int32_t getRegNum() const { return RegNum; }
   void setRegNum(int32_t NewRegNum) {
@@ skipping 50 matching lines @@
   static bool classof(const Operand *Operand) {
     return Operand->getKind() == kVariable;
   }
 
   // The destructor is public because of the asType() method.
   virtual ~Variable() {}
 
 private:
   Variable(Type Ty, const CfgNode *Node, SizeT Index, const IceString &Name)
       : Operand(kVariable, Ty), Number(Index), Name(Name), DefInst(NULL),
-        DefNode(Node), IsArgument(false), StackOffset(0), RegNum(NoRegister),
-        RegNumTmp(NoRegister), Weight(1), RegisterPreference(NULL),
-        AllowRegisterOverlap(false), LoVar(NULL), HiVar(NULL) {
+        DefNode(Node), IsMultidef(false), IsArgument(false), StackOffset(0),
+        RegNum(NoRegister), RegNumTmp(NoRegister), Weight(1),
+        RegisterPreference(NULL), AllowRegisterOverlap(false), LoVar(NULL),
+        HiVar(NULL) {
     Vars = VarsReal;
     Vars[0] = this;
     NumVars = 1;
   }
   Variable(const Variable &) LLVM_DELETED_FUNCTION;
   Variable &operator=(const Variable &) LLVM_DELETED_FUNCTION;
   // Number is unique across all variables, and is used as a
   // (bit)vector index for liveness analysis.
   const SizeT Number;
   // Name is optional.
   IceString Name;
   // DefInst is the instruction that produces this variable as its
   // dest.
   Inst *DefInst;
   // DefNode is the node where this variable was produced, and is
   // reset to NULL if it is used outside that node.  This is used for
   // detecting isMultiblockLife().  TODO: Collapse this to a single
   // bit and use a separate pass to calculate the values across the
   // Cfg.  This saves space in the Variable, and removes the fragility
   // of incrementally computing and maintaining the information.
   const CfgNode *DefNode;
+  bool IsMultidef;
   bool IsArgument;
   // StackOffset is the canonical location on stack (only if
   // RegNum<0 || IsArgument).
   int32_t StackOffset;
   // RegNum is the allocated register, or NoRegister if it isn't
   // register-allocated.
   int32_t RegNum;
   // RegNumTmp is the tentative assignment during register allocation.
   int32_t RegNumTmp;
   RegWeight Weight; // Register allocation priority
@@ skipping 18 matching lines @@
   Variable *LoVar;
   Variable *HiVar;
   // VarsReal (and Operand::Vars) are set up such that Vars[0] ==
   // this.
   Variable *VarsReal[1];
 };
 
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICEOPERAND_H