[turbofan] ARM64 branch selector additions

src/compiler/arm64/instruction-codes-arm64.h

 // Copyright 2014 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #ifndef V8_COMPILER_ARM64_INSTRUCTION_CODES_ARM64_H_
 #define V8_COMPILER_ARM64_INSTRUCTION_CODES_ARM64_H_
 
 namespace v8 {
 namespace internal {
 namespace compiler {
 
 // ARM64-specific opcodes that specify which assembly sequence to emit.
 // Most opcodes specify a single instruction.
 #define TARGET_ARCH_OPCODE_LIST(V) \
   V(Arm64Add)                      \
   V(Arm64Add32)                    \
   V(Arm64And)                      \
   V(Arm64And32)                    \
   V(Arm64Cmp)                      \
   V(Arm64Cmp32)                    \
+  V(Arm64Cmn)                      \
+  V(Arm64Cmn32)                    \
   V(Arm64Tst)                      \
   V(Arm64Tst32)                    \
   V(Arm64Or)                       \
   V(Arm64Or32)                     \
   V(Arm64Xor)                      \
   V(Arm64Xor32)                    \
   V(Arm64Sub)                      \
   V(Arm64Sub32)                    \
   V(Arm64Mul)                      \
   V(Arm64Mul32)                    \
@@ skipping 65 matching lines @@
 // MRR = [register + register]
 #define TARGET_ADDRESSING_MODE_LIST(V) \
   V(MRI) /* [%r0 + K] */               \
   V(MRR) /* [%r0 + %r1] */
 
 }  // namespace internal
 }  // namespace compiler
 }  // namespace v8
 
 #endif  // V8_COMPILER_ARM64_INSTRUCTION_CODES_ARM64_H_