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1 // Copyright 2011 the V8 project authors. All rights reserved. | 1 // Copyright 2011 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 #include <limits.h> | 5 #include <limits.h> |
6 #include <stdarg.h> | 6 #include <stdarg.h> |
7 #include <stdlib.h> | 7 #include <stdlib.h> |
8 #include <cmath> | 8 #include <cmath> |
9 | 9 |
10 #include "src/v8.h" | 10 #include "src/v8.h" |
11 | 11 |
12 #if V8_TARGET_ARCH_MIPS | 12 #if V8_TARGET_ARCH_MIPS |
13 | 13 |
14 #include "src/assembler.h" | 14 #include "src/assembler.h" |
15 #include "src/base/bits.h" | 15 #include "src/base/bits.h" |
16 #include "src/disasm.h" | 16 #include "src/disasm.h" |
17 #include "src/globals.h" // Need the BitCast. | |
18 #include "src/mips/constants-mips.h" | 17 #include "src/mips/constants-mips.h" |
19 #include "src/mips/simulator-mips.h" | 18 #include "src/mips/simulator-mips.h" |
20 #include "src/ostreams.h" | 19 #include "src/ostreams.h" |
21 | 20 |
22 | 21 |
23 // Only build the simulator if not compiling for real MIPS hardware. | 22 // Only build the simulator if not compiling for real MIPS hardware. |
24 #if defined(USE_SIMULATOR) | 23 #if defined(USE_SIMULATOR) |
25 | 24 |
26 namespace v8 { | 25 namespace v8 { |
27 namespace internal { | 26 namespace internal { |
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1119 // Set ONLY upper 32-bits, leaving lower bits untouched. | 1118 // Set ONLY upper 32-bits, leaving lower bits untouched. |
1120 // TODO(plind): big endian issue. | 1119 // TODO(plind): big endian issue. |
1121 DCHECK((fpureg >= 0) && (fpureg < kNumFPURegisters)); | 1120 DCHECK((fpureg >= 0) && (fpureg < kNumFPURegisters)); |
1122 int32_t *phiword = (reinterpret_cast<int32_t*>(&FPUregisters_[fpureg])) + 1; | 1121 int32_t *phiword = (reinterpret_cast<int32_t*>(&FPUregisters_[fpureg])) + 1; |
1123 *phiword = value; | 1122 *phiword = value; |
1124 } | 1123 } |
1125 | 1124 |
1126 | 1125 |
1127 void Simulator::set_fpu_register_float(int fpureg, float value) { | 1126 void Simulator::set_fpu_register_float(int fpureg, float value) { |
1128 DCHECK((fpureg >= 0) && (fpureg < kNumFPURegisters)); | 1127 DCHECK((fpureg >= 0) && (fpureg < kNumFPURegisters)); |
1129 *BitCast<float*>(&FPUregisters_[fpureg]) = value; | 1128 *bit_cast<float*>(&FPUregisters_[fpureg]) = value; |
1130 } | 1129 } |
1131 | 1130 |
1132 | 1131 |
1133 void Simulator::set_fpu_register_double(int fpureg, double value) { | 1132 void Simulator::set_fpu_register_double(int fpureg, double value) { |
1134 if (IsFp64Mode()) { | 1133 if (IsFp64Mode()) { |
1135 DCHECK((fpureg >= 0) && (fpureg < kNumFPURegisters)); | 1134 DCHECK((fpureg >= 0) && (fpureg < kNumFPURegisters)); |
1136 *BitCast<double*>(&FPUregisters_[fpureg]) = value; | 1135 *bit_cast<double*>(&FPUregisters_[fpureg]) = value; |
1137 } else { | 1136 } else { |
1138 DCHECK((fpureg >= 0) && (fpureg < kNumFPURegisters) && ((fpureg % 2) == 0)); | 1137 DCHECK((fpureg >= 0) && (fpureg < kNumFPURegisters) && ((fpureg % 2) == 0)); |
1139 int64_t i64 = BitCast<int64_t>(value); | 1138 int64_t i64 = bit_cast<int64_t>(value); |
1140 set_fpu_register_word(fpureg, i64 & 0xffffffff); | 1139 set_fpu_register_word(fpureg, i64 & 0xffffffff); |
1141 set_fpu_register_word(fpureg + 1, i64 >> 32); | 1140 set_fpu_register_word(fpureg + 1, i64 >> 32); |
1142 } | 1141 } |
1143 } | 1142 } |
1144 | 1143 |
1145 | 1144 |
1146 // Get the register from the architecture state. This function does handle | 1145 // Get the register from the architecture state. This function does handle |
1147 // the special case of accessing the PC register. | 1146 // the special case of accessing the PC register. |
1148 int32_t Simulator::get_register(int reg) const { | 1147 int32_t Simulator::get_register(int reg) const { |
1149 DCHECK((reg >= 0) && (reg < kNumSimuRegisters)); | 1148 DCHECK((reg >= 0) && (reg < kNumSimuRegisters)); |
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1188 | 1187 |
1189 | 1188 |
1190 int32_t Simulator::get_fpu_register_hi_word(int fpureg) const { | 1189 int32_t Simulator::get_fpu_register_hi_word(int fpureg) const { |
1191 DCHECK((fpureg >= 0) && (fpureg < kNumFPURegisters)); | 1190 DCHECK((fpureg >= 0) && (fpureg < kNumFPURegisters)); |
1192 return static_cast<int32_t>((FPUregisters_[fpureg] >> 32) & 0xffffffff); | 1191 return static_cast<int32_t>((FPUregisters_[fpureg] >> 32) & 0xffffffff); |
1193 } | 1192 } |
1194 | 1193 |
1195 | 1194 |
1196 float Simulator::get_fpu_register_float(int fpureg) const { | 1195 float Simulator::get_fpu_register_float(int fpureg) const { |
1197 DCHECK((fpureg >= 0) && (fpureg < kNumFPURegisters)); | 1196 DCHECK((fpureg >= 0) && (fpureg < kNumFPURegisters)); |
1198 return *BitCast<float*>( | 1197 return *bit_cast<float*>(const_cast<int64_t*>(&FPUregisters_[fpureg])); |
1199 const_cast<int64_t*>(&FPUregisters_[fpureg])); | |
1200 } | 1198 } |
1201 | 1199 |
1202 | 1200 |
1203 double Simulator::get_fpu_register_double(int fpureg) const { | 1201 double Simulator::get_fpu_register_double(int fpureg) const { |
1204 if (IsFp64Mode()) { | 1202 if (IsFp64Mode()) { |
1205 DCHECK((fpureg >= 0) && (fpureg < kNumFPURegisters)); | 1203 DCHECK((fpureg >= 0) && (fpureg < kNumFPURegisters)); |
1206 return *BitCast<double*>(&FPUregisters_[fpureg]); | 1204 return *bit_cast<double*>(&FPUregisters_[fpureg]); |
1207 } else { | 1205 } else { |
1208 DCHECK((fpureg >= 0) && (fpureg < kNumFPURegisters) && ((fpureg % 2) == 0)); | 1206 DCHECK((fpureg >= 0) && (fpureg < kNumFPURegisters) && ((fpureg % 2) == 0)); |
1209 int64_t i64; | 1207 int64_t i64; |
1210 i64 = static_cast<uint32_t>(get_fpu_register_word(fpureg)); | 1208 i64 = static_cast<uint32_t>(get_fpu_register_word(fpureg)); |
1211 i64 |= static_cast<uint64_t>(get_fpu_register_word(fpureg + 1)) << 32; | 1209 i64 |= static_cast<uint64_t>(get_fpu_register_word(fpureg + 1)) << 32; |
1212 return BitCast<double>(i64); | 1210 return bit_cast<double>(i64); |
1213 } | 1211 } |
1214 } | 1212 } |
1215 | 1213 |
1216 | 1214 |
1217 // Runtime FP routines take up to two double arguments and zero | 1215 // Runtime FP routines take up to two double arguments and zero |
1218 // or one integer arguments. All are constructed here, | 1216 // or one integer arguments. All are constructed here, |
1219 // from a0-a3 or f12 and f14. | 1217 // from a0-a3 or f12 and f14. |
1220 void Simulator::GetFpArgs(double* x, double* y, int32_t* z) { | 1218 void Simulator::GetFpArgs(double* x, double* y, int32_t* z) { |
1221 if (!IsMipsSoftFloatABI) { | 1219 if (!IsMipsSoftFloatABI) { |
1222 *x = get_fpu_register_double(12); | 1220 *x = get_fpu_register_double(12); |
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3261 } | 3259 } |
3262 | 3260 |
3263 | 3261 |
3264 #undef UNSUPPORTED | 3262 #undef UNSUPPORTED |
3265 | 3263 |
3266 } } // namespace v8::internal | 3264 } } // namespace v8::internal |
3267 | 3265 |
3268 #endif // USE_SIMULATOR | 3266 #endif // USE_SIMULATOR |
3269 | 3267 |
3270 #endif // V8_TARGET_ARCH_MIPS | 3268 #endif // V8_TARGET_ARCH_MIPS |
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