Fix StoreIndexedInstr input representation requirements for Int32/Uint32 arrays.

runtime/vm/assembler_arm.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/globals.h"
 #if defined(TARGET_ARCH_ARM)
 
 #include "vm/assembler.h"
 #include "vm/cpu.h"
 #include "vm/longjump.h"
@@ skipping 2243 matching lines @@
 
 
 void Assembler::Asr(Register rd, Register rm, uint32_t shift_imm,
                     Condition cond) {
   ASSERT(shift_imm != 0);  // Do not use Asr if no shift is wanted.
   if (shift_imm == 32) shift_imm = 0;  // Comply to UAL syntax.
   mov(rd, Operand(rm, ASR, shift_imm), cond);
 }
 
 
+void Assembler::AsrS(Register rd, Register rm, uint32_t shift_imm,
+                     Condition cond) {
+  ASSERT(shift_imm != 0);  // Do not use Asr if no shift is wanted.
+  if (shift_imm == 32) shift_imm = 0;  // Comply to UAL syntax.

[zra, 2014/09/10 23:17:21]

Please use curly braces.

[Vyacheslav Egorov (Google), 2014/09/11 11:49:16]

Done.

+  movs(rd, Operand(rm, ASR, shift_imm), cond);
+}
+
+
 void Assembler::Asr(Register rd, Register rm, Register rs, Condition cond) {
   mov(rd, Operand(rm, ASR, rs), cond);
 }
 
 
 void Assembler::Ror(Register rd, Register rm, uint32_t shift_imm,
                     Condition cond) {
   ASSERT(shift_imm != 0);  // Use Rrx instruction.
   mov(rd, Operand(rm, ROR, shift_imm), cond);
 }
@@ skipping 1101 matching lines @@
 
 
 const char* Assembler::FpuRegisterName(FpuRegister reg) {
   ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters));
   return fpu_reg_names[reg];
 }
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_ARM