Integrate SIMD optimisations for zlib

third_party/zlib/x86.c

Index: third_party/zlib/x86.c
diff --git a/third_party/zlib/x86.c b/third_party/zlib/x86.c
new file mode 100644
index 0000000000000000000000000000000000000000..9feca22f50b749488bd84d589c436b6762cb8086
--- /dev/null
+++ b/third_party/zlib/x86.c
@@ -0,0 +1,57 @@
+/*
+ * x86 feature check
+ *
+ * Copyright (C) 2013 Intel Corporation. All rights reserved.
+ * Author:
+ *  Jim Kukunas
+ * 
+ * For conditions of distribution and use, see copyright notice in zlib.h
+ */
+

[agl, 2014/09/26 18:32:27]

delete line.

[robert.bradford, 2014/10/15 16:14:40]

Done.

+
+#include "x86.h"
+
+#include <pthread.h>

[agl, 2014/09/26 18:32:27]

This file is always built, but includes pthread.h. That'll fail on other
platforms I think.

It would be nice if this file were conditionally compiled and that the stub file
included the dummy x86_check_features.

Note that it shouldn't be conditionally compiled in the zlib_x86_simd library
(although the stub can be in there) because that library may use optional
instructions and this code has to work without them.

[robert.bradford, 2014/10/15 16:14:40]

Works on Mac OS X, for Windows we now have a Win32 api equivalent.
I adopted the model you proposed here with.

+
+int x86_cpu_enable_simd;
+
+#ifdef HAVE_ARCH_INTEL
+pthread_once_t cpu_check_inited_once = PTHREAD_ONCE_INIT;
+static void _x86_check_features(void);
+
+void x86_check_features(void) {
+  pthread_once(&cpu_check_inited_once, _x86_check_features);
+}
+
+static void _x86_check_features(void)
+{
+    int x86_cpu_has_sse2;
+    int x86_cpu_has_sse42;
+    int x86_cpu_has_pclmulqdq;
+    unsigned eax, ebx, ecx, edx;
+
+    eax = 1;
+    __asm__ __volatile__ (
+#ifdef __i386__
+        "xchg %%ebx, %1\n\t"
+#endif
+        "cpuid\n\t"
+#ifdef __i386__
+        "xchg %1, %%ebx\n\t"
+    : "+a" (eax), "=S" (ebx), "=c" (ecx), "=d" (edx)
+#else
+    : "+a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
+#endif
+    );
+
+    x86_cpu_has_sse2 = edx & 0x4000000;
+    x86_cpu_has_sse42 = ecx & 0x100000;
+    x86_cpu_has_pclmulqdq = ecx & 0x2;
+
+    x86_cpu_enable_simd = x86_cpu_has_sse2 &&
+                          x86_cpu_has_sse42 &&
+                          x86_cpu_has_pclmulqdq;
+}
+#else
+void x86_check_features(void) {}
+#endif /* HAVE_ARCH_INTEL */