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Side by Side Diff: third_party/zlib/x86.c

Issue 552123005: Integrate SIMD optimisations for zlib (Closed) Base URL: https://chromium.googlesource.com/chromium/src.git@master
Patch Set: Fix crc_fold_copy to work with inputs where len % 16 > 0 Created 6 years, 2 months ago
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1 /*
2 * x86 feature check
3 *
4 * Copyright (C) 2013 Intel Corporation. All rights reserved.
5 * Author:
6 * Jim Kukunas
7 *
8 * For conditions of distribution and use, see copyright notice in zlib.h
9 */
10
11 #include "x86.h"
12
13 int x86_cpu_enable_simd;
14
15 #ifndef _MSC_VER
16 #include <pthread.h>
17
18 pthread_once_t cpu_check_inited_once = PTHREAD_ONCE_INIT;
19 static void _x86_check_features(void);
20
21 void x86_check_features(void)
22 {
23 pthread_once(&cpu_check_inited_once, _x86_check_features);
24 }
25
26 static void _x86_check_features(void)
27 {
28 int x86_cpu_has_sse2;
29 int x86_cpu_has_sse42;
30 int x86_cpu_has_pclmulqdq;
31 unsigned eax, ebx, ecx, edx;
32
33 eax = 1;
34 #ifdef __i386__
35 __asm__ __volatile__ (
36 "xchg %%ebx, %1\n\t"
37 "cpuid\n\t"
38 "xchg %1, %%ebx\n\t"
39 : "+a" (eax), "=S" (ebx), "=c" (ecx), "=d" (edx)
40 );
41 #else
42 __asm__ __volatile__ (
43 "cpuid\n\t"
44 : "+a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
45 );
46 #endif /* (__i386__) */
47
48 x86_cpu_has_sse2 = edx & 0x4000000;
49 x86_cpu_has_sse42 = ecx & 0x100000;
50 x86_cpu_has_pclmulqdq = ecx & 0x2;
51
52 x86_cpu_enable_simd = x86_cpu_has_sse2 &&
53 x86_cpu_has_sse42 &&
54 x86_cpu_has_pclmulqdq;
55 }
56 #else
57 #include <intrin.h>
58 #include <windows.h>
59
60 static BOOL CALLBACK _x86_check_features(PINIT_ONCE once, PVOID param, PVOID *co ntext);
61 static INIT_ONCE cpu_check_inited_once = INIT_ONCE_STATIC_INIT;
62
63 void x86_check_features(void)
64 {
65 #if (_WIN32_WINNT >= 0x0600)
66 InitOnceExecuteOnce(&cpu_check_inited_once, _x86_check_features, NULL, NULL) ;
67 #endif /* (_WIN32_WINNT >= 0x0600) */
68 }
69
70 #if (_WIN32_WINNT >= 0x0600)
71 static BOOL CALLBACK _x86_check_features(PINIT_ONCE once, PVOID param, PVOID *co ntext)
72 {
73 int x86_cpu_has_sse2;
74 int x86_cpu_has_sse42;
75 int x86_cpu_has_pclmulqdq;
76 int regs[4];
77
78 __cpuid(regs, 1);
79
80 x86_cpu_has_sse2 = regs[3] & 0x4000000;
81 x86_cpu_has_sse42= regs[2] & 0x100000;
82 x86_cpu_has_pclmulqdq = regs[2] & 0x2;
83
84 x86_cpu_enable_simd = x86_cpu_has_sse2 &&
85 x86_cpu_has_sse42 &&
86 x86_cpu_has_pclmulqdq;
87 return TRUE;
88 }
89 #endif /* (_WIN32_WINNT >= 0x0600) */
90 #endif /* _MSC_VER */
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