Reland r23732: ARM64: Fix and improve --trace-sim register trace.

src/arm64/simulator-arm64.cc

 // Copyright 2013 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include <stdlib.h>
 #include <cmath>
 #include <cstdarg>
 #include "src/v8.h"
 
 #if V8_TARGET_ARCH_ARM64
@@ skipping 12 matching lines @@
 
 
 // This macro provides a platform independent use of sscanf. The reason for
 // SScanF not being implemented in a platform independent way through
 // ::v8::internal::OS in the same way as SNPrintF is that the
 // Windows C Run-Time Library does not provide vsscanf.
 #define SScanF sscanf  // NOLINT
 
 
 // Helpers for colors.
-// Depending on your terminal configuration, the colour names may not match the
-// observed colours.
-#define COLOUR(colour_code)  "\033[" colour_code "m"
-#define BOLD(colour_code)    "1;" colour_code
-#define NORMAL ""
-#define GREY   "30"
-#define GREEN  "32"
-#define ORANGE "33"
-#define BLUE   "34"
-#define PURPLE "35"
-#define INDIGO "36"
-#define WHITE  "37"
+#define COLOUR(colour_code)       "\033[0;" colour_code "m"
+#define COLOUR_BOLD(colour_code)  "\033[1;" colour_code "m"
+#define NORMAL  ""
+#define GREY    "30"
+#define RED     "31"
+#define GREEN   "32"
+#define YELLOW  "33"
+#define BLUE    "34"
+#define MAGENTA "35"
+#define CYAN    "36"
+#define WHITE   "37"
 typedef char const * const TEXT_COLOUR;
 TEXT_COLOUR clr_normal         = FLAG_log_colour ? COLOUR(NORMAL)       : "";
-TEXT_COLOUR clr_flag_name      = FLAG_log_colour ? COLOUR(BOLD(GREY))   : "";
-TEXT_COLOUR clr_flag_value     = FLAG_log_colour ? COLOUR(BOLD(WHITE))  : "";
-TEXT_COLOUR clr_reg_name       = FLAG_log_colour ? COLOUR(BOLD(BLUE))   : "";
-TEXT_COLOUR clr_reg_value      = FLAG_log_colour ? COLOUR(BOLD(INDIGO)) : "";
-TEXT_COLOUR clr_fpreg_name     = FLAG_log_colour ? COLOUR(BOLD(ORANGE)) : "";
-TEXT_COLOUR clr_fpreg_value    = FLAG_log_colour ? COLOUR(BOLD(PURPLE)) : "";
-TEXT_COLOUR clr_memory_value   = FLAG_log_colour ? COLOUR(BOLD(GREEN))  : "";
-TEXT_COLOUR clr_memory_address = FLAG_log_colour ? COLOUR(GREEN)        : "";
-TEXT_COLOUR clr_debug_number   = FLAG_log_colour ? COLOUR(BOLD(ORANGE)) : "";
-TEXT_COLOUR clr_debug_message  = FLAG_log_colour ? COLOUR(ORANGE)       : "";
+TEXT_COLOUR clr_flag_name      = FLAG_log_colour ? COLOUR_BOLD(WHITE)   : "";
+TEXT_COLOUR clr_flag_value     = FLAG_log_colour ? COLOUR(NORMAL)       : "";
+TEXT_COLOUR clr_reg_name       = FLAG_log_colour ? COLOUR_BOLD(CYAN)    : "";
+TEXT_COLOUR clr_reg_value      = FLAG_log_colour ? COLOUR(CYAN)         : "";
+TEXT_COLOUR clr_fpreg_name     = FLAG_log_colour ? COLOUR_BOLD(MAGENTA) : "";
+TEXT_COLOUR clr_fpreg_value    = FLAG_log_colour ? COLOUR(MAGENTA)      : "";
+TEXT_COLOUR clr_memory_address = FLAG_log_colour ? COLOUR_BOLD(BLUE)    : "";
+TEXT_COLOUR clr_debug_number   = FLAG_log_colour ? COLOUR_BOLD(YELLOW)  : "";
+TEXT_COLOUR clr_debug_message  = FLAG_log_colour ? COLOUR(YELLOW)       : "";
 TEXT_COLOUR clr_printf         = FLAG_log_colour ? COLOUR(GREEN)        : "";
 
 
 // This is basically the same as PrintF, with a guard for FLAG_trace_sim.
 void Simulator::TraceSim(const char* format, ...) {
   if (FLAG_trace_sim) {
     va_list arguments;
     va_start(arguments, format);
     base::OS::VFPrint(stream_, format, arguments);
     va_end(arguments);
@@ skipping 263 matching lines @@
   DCHECK(sizeof(uintptr_t) < 2 * kXRegSize);
   set_sp(current_sp + 2 * kXRegSize);
   return address;
 }
 
 
 // Returns the limit of the stack area to enable checking for stack overflows.
 uintptr_t Simulator::StackLimit() const {
   // Leave a safety margin of 1024 bytes to prevent overrunning the stack when
   // pushing values.
-  return reinterpret_cast<uintptr_t>(stack_limit_) + 1024;
+  return stack_limit_ + 1024;
 }
 
 
 Simulator::Simulator(Decoder<DispatchingDecoderVisitor>* decoder,
                      Isolate* isolate, FILE* stream)
     : decoder_(decoder),
       last_debugger_input_(NULL),
       log_parameters_(NO_PARAM),
       isolate_(isolate) {
   // Setup the decoder.
@@ skipping 22 matching lines @@
   Init(stdout);
   CHECK(!FLAG_trace_sim && !FLAG_log_instruction_stats);
 }
 
 
 void Simulator::Init(FILE* stream) {
   ResetState();
 
   // Allocate and setup the simulator stack.
   stack_size_ = (FLAG_sim_stack_size * KB) + (2 * stack_protection_size_);
-  stack_ = new byte[stack_size_];
+  stack_ = reinterpret_cast<uintptr_t>(new byte[stack_size_]);
   stack_limit_ = stack_ + stack_protection_size_;
-  byte* tos = stack_ + stack_size_ - stack_protection_size_;
-  // The stack pointer must be 16 bytes aligned.
-  set_sp(reinterpret_cast<int64_t>(tos) & ~0xfUL);
+  uintptr_t tos = stack_ + stack_size_ - stack_protection_size_;
+  // The stack pointer must be 16-byte aligned.
+  set_sp(tos & ~0xfUL);
 
   stream_ = stream;
   print_disasm_ = new PrintDisassembler(stream_);
 
   // The debugger needs to disassemble code without the simulator executing an
   // instruction, so we create a dedicated decoder.
   disassembler_decoder_ = new Decoder<DispatchingDecoderVisitor>();
   disassembler_decoder_->AppendVisitor(print_disasm_);
 }
 
@@ skipping 15 matching lines @@
   // Returning to address 0 exits the Simulator.
   set_lr(kEndOfSimAddress);
 
   // Reset debug helpers.
   breakpoints_.empty();
   break_on_next_= false;
 }
 
 
 Simulator::~Simulator() {
-  delete[] stack_;
+  delete[] reinterpret_cast<byte*>(stack_);
   if (FLAG_log_instruction_stats) {
     delete instrument_;
   }
   delete disassembler_decoder_;
   delete print_disasm_;
   DeleteArray(last_debugger_input_);
   delete decoder_;
 }
 
 
@@ skipping 293 matching lines @@
 
 
 void* Simulator::RedirectExternalReference(void* external_function,
                                            ExternalReference::Type type) {
   Redirection* redirection = Redirection::Get(external_function, type);
   return redirection->address_of_redirect_call();
 }
 
 
 const char* Simulator::xreg_names[] = {
-"x0",  "x1",  "x2",  "x3",  "x4",  "x5",  "x6",  "x7",
-"x8",  "x9",  "x10", "x11", "x12", "x13", "x14", "x15",
-"ip0", "ip1", "x18", "x19", "x20", "x21", "x22", "x23",
-"x24", "x25", "x26", "cp", "jssp", "fp", "lr",  "xzr", "csp"};
+"x0",  "x1",  "x2",  "x3",  "x4",   "x5",  "x6",  "x7",
+"x8",  "x9",  "x10", "x11", "x12",  "x13", "x14", "x15",
+"ip0", "ip1", "x18", "x19", "x20",  "x21", "x22", "x23",
+"x24", "x25", "x26", "cp",  "jssp", "fp",  "lr",  "xzr", "csp"};
 
 const char* Simulator::wreg_names[] = {
-"w0",  "w1",  "w2",  "w3",  "w4",  "w5",  "w6",  "w7",
-"w8",  "w9",  "w10", "w11", "w12", "w13", "w14", "w15",
-"w16", "w17", "w18", "w19", "w20", "w21", "w22", "w23",
+"w0",  "w1",  "w2",  "w3",  "w4",    "w5",  "w6",  "w7",
+"w8",  "w9",  "w10", "w11", "w12",   "w13", "w14", "w15",
+"w16", "w17", "w18", "w19", "w20",   "w21", "w22", "w23",
 "w24", "w25", "w26", "wcp", "wjssp", "wfp", "wlr", "wzr", "wcsp"};
 
 const char* Simulator::sreg_names[] = {
 "s0",  "s1",  "s2",  "s3",  "s4",  "s5",  "s6",  "s7",
 "s8",  "s9",  "s10", "s11", "s12", "s13", "s14", "s15",
 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31"};
 
 const char* Simulator::dreg_names[] = {
 "d0",  "d1",  "d2",  "d3",  "d4",  "d5",  "d6",  "d7",
 "d8",  "d9",  "d10", "d11", "d12", "d13", "d14", "d15",
 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31"};
 
 const char* Simulator::vreg_names[] = {
 "v0",  "v1",  "v2",  "v3",  "v4",  "v5",  "v6",  "v7",
 "v8",  "v9",  "v10", "v11", "v12", "v13", "v14", "v15",
 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"};
 
 
 const char* Simulator::WRegNameForCode(unsigned code, Reg31Mode mode) {
+  STATIC_ASSERT(arraysize(Simulator::wreg_names) == (kNumberOfRegisters + 1));
   DCHECK(code < kNumberOfRegisters);
+  // The modulo operator has no effect here, but it silences a broken GCC
+  // warning about out-of-bounds array accesses.
+  code %= kNumberOfRegisters;
+
   // If the code represents the stack pointer, index the name after zr.
   if ((code == kZeroRegCode) && (mode == Reg31IsStackPointer)) {
     code = kZeroRegCode + 1;
   }
   return wreg_names[code];
 }
 
 
 const char* Simulator::XRegNameForCode(unsigned code, Reg31Mode mode) {
+  STATIC_ASSERT(arraysize(Simulator::xreg_names) == (kNumberOfRegisters + 1));
   DCHECK(code < kNumberOfRegisters);
+  code %= kNumberOfRegisters;
+
   // If the code represents the stack pointer, index the name after zr.
   if ((code == kZeroRegCode) && (mode == Reg31IsStackPointer)) {
     code = kZeroRegCode + 1;
   }
   return xreg_names[code];
 }
 
 
 const char* Simulator::SRegNameForCode(unsigned code) {
+  STATIC_ASSERT(arraysize(Simulator::sreg_names) == kNumberOfFPRegisters);
   DCHECK(code < kNumberOfFPRegisters);
-  return sreg_names[code];
+  return sreg_names[code % kNumberOfFPRegisters];
 }
 
 
 const char* Simulator::DRegNameForCode(unsigned code) {
+  STATIC_ASSERT(arraysize(Simulator::dreg_names) == kNumberOfFPRegisters);
   DCHECK(code < kNumberOfFPRegisters);
-  return dreg_names[code];
+  return dreg_names[code % kNumberOfFPRegisters];
 }
 
 
 const char* Simulator::VRegNameForCode(unsigned code) {
+  STATIC_ASSERT(arraysize(Simulator::vreg_names) == kNumberOfFPRegisters);
   DCHECK(code < kNumberOfFPRegisters);
-  return vreg_names[code];
+  return vreg_names[code % kNumberOfFPRegisters];
 }
 
 
 int Simulator::CodeFromName(const char* name) {
   for (unsigned i = 0; i < kNumberOfRegisters; i++) {
     if ((strcmp(xreg_names[i], name) == 0) ||
         (strcmp(wreg_names[i], name) == 0)) {
       return i;
     }
   }
@@ skipping 36 matching lines @@
   V = ((src1 ^ src2) >= 0) && ((src1 ^ result) < 0);
 
   N = CalcNFlag(result);
   Z = CalcZFlag(result);
 
   if (set_flags) {
     nzcv().SetN(N);
     nzcv().SetZ(Z);
     nzcv().SetC(C);
     nzcv().SetV(V);
+    LogSystemRegister(NZCV);
   }
   return result;
 }
 
 
 template<typename T>
 void Simulator::AddSubWithCarry(Instruction* instr) {
   T op2 = reg<T>(instr->Rm());
   T new_val;
 
@@ skipping 103 matching lines @@
     nzcv().SetRawValue(FPUnorderedFlag);
   } else if (val0 < val1) {
     nzcv().SetRawValue(FPLessThanFlag);
   } else if (val0 > val1) {
     nzcv().SetRawValue(FPGreaterThanFlag);
   } else if (val0 == val1) {
     nzcv().SetRawValue(FPEqualFlag);
   } else {
     UNREACHABLE();
   }
+  LogSystemRegister(NZCV);
 }
 
 
 void Simulator::SetBreakpoint(Instruction* location) {
   for (unsigned i = 0; i < breakpoints_.size(); i++) {
     if (breakpoints_.at(i).location == location) {
       PrintF(stream_,
              "Existing breakpoint at %p was %s\n",
              reinterpret_cast<void*>(location),
              breakpoints_.at(i).enabled ? "disabled" : "enabled");
@@ skipping 46 matching lines @@
 
 
 void Simulator::PrintInstructionsAt(Instruction* start, uint64_t count) {
   Instruction* end = start->InstructionAtOffset(count * kInstructionSize);
   for (Instruction* pc = start; pc < end; pc = pc->following()) {
     disassembler_decoder_->Decode(pc);
   }
 }
 
 
-void Simulator::PrintSystemRegisters(bool print_all) {
-  static bool first_run = true;
-
-  static SimSystemRegister last_nzcv;
-  if (print_all || first_run || (last_nzcv.RawValue() != nzcv().RawValue())) {
-    fprintf(stream_, "# %sFLAGS: %sN:%d Z:%d C:%d V:%d%s\n",
-            clr_flag_name,
-            clr_flag_value,
-            nzcv().N(), nzcv().Z(), nzcv().C(), nzcv().V(),
-            clr_normal);
-  }
-  last_nzcv = nzcv();
-
-  static SimSystemRegister last_fpcr;
-  if (print_all || first_run || (last_fpcr.RawValue() != fpcr().RawValue())) {
-    static const char * rmode[] = {
-      "0b00 (Round to Nearest)",
-      "0b01 (Round towards Plus Infinity)",
-      "0b10 (Round towards Minus Infinity)",
-      "0b11 (Round towards Zero)"
-    };
-    DCHECK(fpcr().RMode() < arraysize(rmode));
-    fprintf(stream_, "# %sFPCR: %sAHP:%d DN:%d FZ:%d RMode:%s%s\n",
-            clr_flag_name,
-            clr_flag_value,
-            fpcr().AHP(), fpcr().DN(), fpcr().FZ(), rmode[fpcr().RMode()],
-            clr_normal);
-  }
-  last_fpcr = fpcr();
-
-  first_run = false;
-}
-
-
-void Simulator::PrintRegisters(bool print_all_regs) {
-  static bool first_run = true;
-  static int64_t last_regs[kNumberOfRegisters];
-
+void Simulator::PrintSystemRegisters() {
+  PrintSystemRegister(NZCV);
+  PrintSystemRegister(FPCR);
+}
+
+
+void Simulator::PrintRegisters() {
   for (unsigned i = 0; i < kNumberOfRegisters; i++) {
-    if (print_all_regs || first_run ||
-        (last_regs[i] != xreg(i, Reg31IsStackPointer))) {
+    PrintRegister(i);
+  }
+}
+
+
+void Simulator::PrintFPRegisters() {
+  for (unsigned i = 0; i < kNumberOfFPRegisters; i++) {
+    PrintFPRegister(i);
+  }
+}
+
+
+void Simulator::PrintRegister(unsigned code, Reg31Mode r31mode) {
+  // Don't print writes into xzr.
+  if ((code == kZeroRegCode) && (r31mode == Reg31IsZeroRegister)) {
+    return;
+  }
+
+  // The template is "# x<code>:value".
+  fprintf(stream_, "# %s%5s: %s0x%016" PRIx64 "%s\n",
+          clr_reg_name, XRegNameForCode(code, r31mode),
+          clr_reg_value, reg<uint64_t>(code, r31mode), clr_normal);
+}
+
+
+void Simulator::PrintFPRegister(unsigned code, PrintFPRegisterSizes sizes) {
+  // The template is "# v<code>:bits (d<code>:value, ...)".
+
+  DCHECK(sizes != 0);
+  DCHECK((sizes & kPrintAllFPRegValues) == sizes);
+
+  // Print the raw bits.
+  fprintf(stream_, "# %s%5s: %s0x%016" PRIx64 "%s (",
+          clr_fpreg_name, VRegNameForCode(code),
+          clr_fpreg_value, fpreg<uint64_t>(code), clr_normal);
+
+  // Print all requested value interpretations.
+  bool need_separator = false;
+  if (sizes & kPrintDRegValue) {
+    fprintf(stream_, "%s%s%s: %s%g%s",
+            need_separator ? ", " : "",
+            clr_fpreg_name, DRegNameForCode(code),
+            clr_fpreg_value, fpreg<double>(code), clr_normal);
+    need_separator = true;
+  }
+
+  if (sizes & kPrintSRegValue) {
+    fprintf(stream_, "%s%s%s: %s%g%s",
+            need_separator ? ", " : "",
+            clr_fpreg_name, SRegNameForCode(code),
+            clr_fpreg_value, fpreg<float>(code), clr_normal);
+    need_separator = true;
+  }
+
+  // End the value list.
+  fprintf(stream_, ")\n");
+}
+
+
+void Simulator::PrintSystemRegister(SystemRegister id) {
+  switch (id) {
+    case NZCV:
+      fprintf(stream_, "# %sNZCV: %sN:%d Z:%d C:%d V:%d%s\n",
+              clr_flag_name, clr_flag_value,
+              nzcv().N(), nzcv().Z(), nzcv().C(), nzcv().V(),
+              clr_normal);
+      break;
+    case FPCR: {
+      static const char * rmode[] = {
+        "0b00 (Round to Nearest)",
+        "0b01 (Round towards Plus Infinity)",
+        "0b10 (Round towards Minus Infinity)",
+        "0b11 (Round towards Zero)"
+      };
+      DCHECK(fpcr().RMode() < arraysize(rmode));
       fprintf(stream_,
-              "# %s%4s:%s 0x%016" PRIx64 "%s\n",
-              clr_reg_name,
-              XRegNameForCode(i, Reg31IsStackPointer),
-              clr_reg_value,
-              xreg(i, Reg31IsStackPointer),
+              "# %sFPCR: %sAHP:%d DN:%d FZ:%d RMode:%s%s\n",
+              clr_flag_name, clr_flag_value,
+              fpcr().AHP(), fpcr().DN(), fpcr().FZ(), rmode[fpcr().RMode()],
               clr_normal);
+      break;
     }
-    // Cache the new register value so the next run can detect any changes.
-    last_regs[i] = xreg(i, Reg31IsStackPointer);
-  }
-  first_run = false;
-}
-
-
-void Simulator::PrintFPRegisters(bool print_all_regs) {
-  static bool first_run = true;
-  static uint64_t last_regs[kNumberOfFPRegisters];
-
-  // Print as many rows of registers as necessary, keeping each individual
-  // register in the same column each time (to make it easy to visually scan
-  // for changes).
-  for (unsigned i = 0; i < kNumberOfFPRegisters; i++) {
-    if (print_all_regs || first_run || (last_regs[i] != dreg_bits(i))) {
-      fprintf(stream_,
-              "# %s %4s:%s 0x%016" PRIx64 "%s (%s%s:%s %g%s %s:%s %g%s)\n",
-              clr_fpreg_name,
-              VRegNameForCode(i),
-              clr_fpreg_value,
-              dreg_bits(i),
-              clr_normal,
-              clr_fpreg_name,
-              DRegNameForCode(i),
-              clr_fpreg_value,
-              dreg(i),
-              clr_fpreg_name,
-              SRegNameForCode(i),
-              clr_fpreg_value,
-              sreg(i),
-              clr_normal);
-    }
-    // Cache the new register value so the next run can detect any changes.
-    last_regs[i] = dreg_bits(i);
-  }
-  first_run = false;
-}
-
-
-void Simulator::PrintProcessorState() {
-  PrintSystemRegisters();
-  PrintRegisters();
-  PrintFPRegisters();
-}
-
-
-void Simulator::PrintWrite(uintptr_t address, uint64_t value,
-                           unsigned num_bytes) {
-  // The template is "# value -> address". The format string is not used
-  // directly in the printf because some compilers struggle with the
-  // parametrized width field (%0*).
-  const char* format = "# %s0x%0*" PRIx64 "%s -> %s0x%016" PRIxPTR "%s\n";
-  fprintf(stream_,
-          format,
-          clr_memory_value,
-          num_bytes * 2,      // The width in hexadecimal characters.
-          value,
-          clr_normal,
-          clr_memory_address,
-          address,
-          clr_normal);
-}
-
-
+    default:
+      UNREACHABLE();
+  }
+}
+
+
+void Simulator::PrintRead(uintptr_t address,
+                          size_t size,
+                          unsigned reg_code) {
+  USE(size);  // Size is unused here.
+
+  // The template is "# x<code>:value <- address".
+  fprintf(stream_, "# %s%5s: %s0x%016" PRIx64 "%s",
+          clr_reg_name, XRegNameForCode(reg_code),
+          clr_reg_value, reg<uint64_t>(reg_code), clr_normal);
+
+  fprintf(stream_, " <- %s0x%016" PRIxPTR "%s\n",
+          clr_memory_address, address, clr_normal);
+}
+
+
+void Simulator::PrintReadFP(uintptr_t address,
+                            size_t size,
+                            unsigned reg_code) {
+  // The template is "# reg:bits (reg:value) <- address".
+  switch (size) {
+    case kSRegSize:
+      fprintf(stream_, "# %s%5s: %s0x%016" PRIx64 "%s (%s%s: %s%gf%s)",
+              clr_fpreg_name, VRegNameForCode(reg_code),
+              clr_fpreg_value, fpreg<uint64_t>(reg_code), clr_normal,
+              clr_fpreg_name, SRegNameForCode(reg_code),
+              clr_fpreg_value, fpreg<float>(reg_code), clr_normal);
+      break;
+    case kDRegSize:
+      fprintf(stream_, "# %s%5s: %s0x%016" PRIx64 "%s (%s%s: %s%g%s)",
+              clr_fpreg_name, VRegNameForCode(reg_code),
+              clr_fpreg_value, fpreg<uint64_t>(reg_code), clr_normal,
+              clr_fpreg_name, DRegNameForCode(reg_code),
+              clr_fpreg_value, fpreg<double>(reg_code), clr_normal);
+      break;
+    default:
+      UNREACHABLE();
+  }
+
+  fprintf(stream_, " <- %s0x%016" PRIxPTR "%s\n",
+          clr_memory_address, address, clr_normal);
+}
+
+
+void Simulator::PrintWrite(uintptr_t address,
+                           size_t size,
+                           unsigned reg_code) {
+  // The template is "# reg:value -> address". To keep the trace tidy and
+  // readable, the value is aligned with the values in the register trace.
+  switch (size) {
+    case kByteSizeInBytes:
+      fprintf(stream_, "# %s%5s<7:0>:          %s0x%02" PRIx8 "%s",
+              clr_reg_name, WRegNameForCode(reg_code),
+              clr_reg_value, reg<uint8_t>(reg_code), clr_normal);
+      break;
+    case kHalfWordSizeInBytes:
+      fprintf(stream_, "# %s%5s<15:0>:       %s0x%04" PRIx16 "%s",
+              clr_reg_name, WRegNameForCode(reg_code),
+              clr_reg_value, reg<uint16_t>(reg_code), clr_normal);
+      break;
+    case kWRegSize:
+      fprintf(stream_, "# %s%5s:         %s0x%08" PRIx32 "%s",
+              clr_reg_name, WRegNameForCode(reg_code),
+              clr_reg_value, reg<uint32_t>(reg_code), clr_normal);
+      break;
+    case kXRegSize:
+      fprintf(stream_, "# %s%5s: %s0x%016" PRIx64 "%s",
+              clr_reg_name, XRegNameForCode(reg_code),
+              clr_reg_value, reg<uint64_t>(reg_code), clr_normal);
+      break;
+    default:
+      UNREACHABLE();
+  }
+
+  fprintf(stream_, " -> %s0x%016" PRIxPTR "%s\n",
+          clr_memory_address, address, clr_normal);
+}
+
+
+void Simulator::PrintWriteFP(uintptr_t address,
+                             size_t size,
+                             unsigned reg_code) {
+  // The template is "# reg:bits (reg:value) -> address". To keep the trace tidy
+  // and readable, the value is aligned with the values in the register trace.
+  switch (size) {
+    case kSRegSize:
+      fprintf(stream_, "# %s%5s<31:0>:   %s0x%08" PRIx32 "%s (%s%s: %s%gf%s)",
+              clr_fpreg_name, VRegNameForCode(reg_code),
+              clr_fpreg_value, fpreg<uint32_t>(reg_code), clr_normal,
+              clr_fpreg_name, SRegNameForCode(reg_code),
+              clr_fpreg_value, fpreg<float>(reg_code), clr_normal);
+      break;
+    case kDRegSize:
+      fprintf(stream_, "# %s%5s: %s0x%016" PRIx64 "%s (%s%s: %s%g%s)",
+              clr_fpreg_name, VRegNameForCode(reg_code),
+              clr_fpreg_value, fpreg<uint64_t>(reg_code), clr_normal,
+              clr_fpreg_name, DRegNameForCode(reg_code),
+              clr_fpreg_value, fpreg<double>(reg_code), clr_normal);
+      break;
+    default:
+      UNREACHABLE();
+  }
+
+  fprintf(stream_, " -> %s0x%016" PRIxPTR "%s\n",
+          clr_memory_address, address, clr_normal);
+}
+
+
 // Visitors---------------------------------------------------------------------
 
 void Simulator::VisitUnimplemented(Instruction* instr) {
   fprintf(stream_, "Unimplemented instruction at %p: 0x%08" PRIx32 "\n",
           reinterpret_cast<void*>(instr), instr->InstructionBits());
   UNIMPLEMENTED();
 }
 
 
 void Simulator::VisitUnallocated(Instruction* instr) {
@@ skipping 205 matching lines @@
     case EOR: result = op1 ^ op2; break;
     default:
       UNIMPLEMENTED();
   }
 
   if (update_flags) {
     nzcv().SetN(CalcNFlag(result));
     nzcv().SetZ(CalcZFlag(result));
     nzcv().SetC(0);
     nzcv().SetV(0);
+    LogSystemRegister(NZCV);
   }
 
   set_reg<T>(instr->Rd(), result, instr->RdMode());
 }
 
 
 void Simulator::VisitConditionalCompareRegister(Instruction* instr) {
   if (instr->SixtyFourBits()) {
     ConditionalCompareHelper(instr, xreg(instr->Rm()));
   } else {
@@ skipping 20 matching lines @@
     // the operands.
     if (instr->Mask(ConditionalCompareMask) == CCMP) {
       AddWithCarry<T>(true, op1, ~op2, 1);
     } else {
       DCHECK(instr->Mask(ConditionalCompareMask) == CCMN);
       AddWithCarry<T>(true, op1, op2, 0);
     }
   } else {
     // If the condition fails, set the status flags to the nzcv immediate.
     nzcv().SetFlags(instr->Nzcv());
+    LogSystemRegister(NZCV);
   }
 }
 
 
 void Simulator::VisitLoadStoreUnsignedOffset(Instruction* instr) {
   int offset = instr->ImmLSUnsigned() << instr->SizeLS();
   LoadStoreHelper(instr, offset, Offset);
 }
 
 
@@ skipping 20 matching lines @@
   int64_t offset = ExtendValue(xreg(instr->Rm()), ext, shift_amount);
   LoadStoreHelper(instr, offset, Offset);
 }
 
 
 void Simulator::LoadStoreHelper(Instruction* instr,
                                 int64_t offset,
                                 AddrMode addrmode) {
   unsigned srcdst = instr->Rt();
   unsigned addr_reg = instr->Rn();
-  uint8_t* address = LoadStoreAddress(addr_reg, offset, addrmode);
-  uint8_t* stack = NULL;
+  uintptr_t address = LoadStoreAddress(addr_reg, offset, addrmode);
+  uintptr_t stack = 0;
 
   // Handle the writeback for stores before the store. On a CPU the writeback
   // and the store are atomic, but when running on the simulator it is possible
   // to be interrupted in between. The simulator is not thread safe and V8 does
   // not require it to be to run JavaScript therefore the profiler may sample
   // the "simulated" CPU in the middle of load/store with writeback. The code
   // below ensures that push operations are safe even when interrupted: the
   // stack pointer will be decremented before adding an element to the stack.
   if (instr->IsStore()) {
     LoadStoreWriteBack(addr_reg, offset, addrmode);
 
     // For store the address post writeback is used to check access below the
     // stack.
-    stack = reinterpret_cast<uint8_t*>(sp());
+    stack = sp();
   }
 
   LoadStoreOp op = static_cast<LoadStoreOp>(instr->Mask(LoadStoreOpMask));
   switch (op) {
-    case LDRB_w:  set_wreg(srcdst, MemoryRead<uint8_t>(address)); break;
-    case LDRH_w:  set_wreg(srcdst, MemoryRead<uint16_t>(address)); break;
-    case LDR_w:   set_wreg(srcdst, MemoryRead<uint32_t>(address)); break;
-    case LDR_x:   set_xreg(srcdst, MemoryRead<uint64_t>(address)); break;
-    case LDRSB_w: set_wreg(srcdst, MemoryRead<int8_t>(address)); break;
-    case LDRSH_w: set_wreg(srcdst, MemoryRead<int16_t>(address)); break;
-    case LDRSB_x: set_xreg(srcdst, MemoryRead<int8_t>(address)); break;
-    case LDRSH_x: set_xreg(srcdst, MemoryRead<int16_t>(address)); break;
-    case LDRSW_x: set_xreg(srcdst, MemoryRead<int32_t>(address)); break;
-    case LDR_s:   set_sreg(srcdst, MemoryRead<float>(address)); break;
-    case LDR_d:   set_dreg(srcdst, MemoryRead<double>(address)); break;
+    // Use _no_log variants to suppress the register trace (LOG_REGS,
+    // LOG_FP_REGS). We will print a more detailed log.
+    case LDRB_w:  set_wreg_no_log(srcdst, MemoryRead<uint8_t>(address)); break;
+    case LDRH_w:  set_wreg_no_log(srcdst, MemoryRead<uint16_t>(address)); break;
+    case LDR_w:   set_wreg_no_log(srcdst, MemoryRead<uint32_t>(address)); break;
+    case LDR_x:   set_xreg_no_log(srcdst, MemoryRead<uint64_t>(address)); break;
+    case LDRSB_w: set_wreg_no_log(srcdst, MemoryRead<int8_t>(address)); break;
+    case LDRSH_w: set_wreg_no_log(srcdst, MemoryRead<int16_t>(address)); break;
+    case LDRSB_x: set_xreg_no_log(srcdst, MemoryRead<int8_t>(address)); break;
+    case LDRSH_x: set_xreg_no_log(srcdst, MemoryRead<int16_t>(address)); break;
+    case LDRSW_x: set_xreg_no_log(srcdst, MemoryRead<int32_t>(address)); break;
+    case LDR_s:   set_sreg_no_log(srcdst, MemoryRead<float>(address)); break;
+    case LDR_d:   set_dreg_no_log(srcdst, MemoryRead<double>(address)); break;
 
     case STRB_w:  MemoryWrite<uint8_t>(address, wreg(srcdst)); break;
     case STRH_w:  MemoryWrite<uint16_t>(address, wreg(srcdst)); break;
     case STR_w:   MemoryWrite<uint32_t>(address, wreg(srcdst)); break;
     case STR_x:   MemoryWrite<uint64_t>(address, xreg(srcdst)); break;
     case STR_s:   MemoryWrite<float>(address, sreg(srcdst)); break;
     case STR_d:   MemoryWrite<double>(address, dreg(srcdst)); break;
 
     default: UNIMPLEMENTED();
   }
 
+  // Print a detailed trace (including the memory address) instead of the basic
+  // register:value trace generated by set_*reg().
+  size_t access_size = 1 << instr->SizeLS();
+  if (instr->IsLoad()) {
+    if ((op == LDR_s) || (op == LDR_d)) {
+      LogReadFP(address, access_size, srcdst);
+    } else {
+      LogRead(address, access_size, srcdst);
+    }
+  } else {
+    if ((op == STR_s) || (op == STR_d)) {
+      LogWriteFP(address, access_size, srcdst);
+    } else {
+      LogWrite(address, access_size, srcdst);
+    }
+  }
+
   // Handle the writeback for loads after the load to ensure safe pop
   // operation even when interrupted in the middle of it. The stack pointer
   // is only updated after the load so pop(fp) will never break the invariant
   // sp <= fp expected while walking the stack in the sampler.
   if (instr->IsLoad()) {
     // For loads the address pre writeback is used to check access below the
     // stack.
-    stack = reinterpret_cast<uint8_t*>(sp());
+    stack = sp();
 
     LoadStoreWriteBack(addr_reg, offset, addrmode);
   }
 
   // Accesses below the stack pointer (but above the platform stack limit) are
   // not allowed in the ABI.
   CheckMemoryAccess(address, stack);
 }
 
 
@@ skipping 15 matching lines @@
 void Simulator::VisitLoadStorePairNonTemporal(Instruction* instr) {
   LoadStorePairHelper(instr, Offset);
 }
 
 
 void Simulator::LoadStorePairHelper(Instruction* instr,
                                     AddrMode addrmode) {
   unsigned rt = instr->Rt();
   unsigned rt2 = instr->Rt2();
   unsigned addr_reg = instr->Rn();
-  int offset = instr->ImmLSPair() << instr->SizeLSPair();
-  uint8_t* address = LoadStoreAddress(addr_reg, offset, addrmode);
-  uint8_t* stack = NULL;
+  size_t access_size = 1 << instr->SizeLSPair();
+  int64_t offset = instr->ImmLSPair() * access_size;
+  uintptr_t address = LoadStoreAddress(addr_reg, offset, addrmode);
+  uintptr_t address2 = address + access_size;
+  uintptr_t stack = 0;
 
   // Handle the writeback for stores before the store. On a CPU the writeback
   // and the store are atomic, but when running on the simulator it is possible
   // to be interrupted in between. The simulator is not thread safe and V8 does
   // not require it to be to run JavaScript therefore the profiler may sample
   // the "simulated" CPU in the middle of load/store with writeback. The code
   // below ensures that push operations are safe even when interrupted: the
   // stack pointer will be decremented before adding an element to the stack.
   if (instr->IsStore()) {
     LoadStoreWriteBack(addr_reg, offset, addrmode);
 
     // For store the address post writeback is used to check access below the
     // stack.
-    stack = reinterpret_cast<uint8_t*>(sp());
+    stack = sp();
   }
 
   LoadStorePairOp op =
     static_cast<LoadStorePairOp>(instr->Mask(LoadStorePairMask));
 
   // 'rt' and 'rt2' can only be aliased for stores.
   DCHECK(((op & LoadStorePairLBit) == 0) || (rt != rt2));
 
   switch (op) {
+    // Use _no_log variants to suppress the register trace (LOG_REGS,
+    // LOG_FP_REGS). We will print a more detailed log.
     case LDP_w: {
-      set_wreg(rt, MemoryRead<uint32_t>(address));
-      set_wreg(rt2, MemoryRead<uint32_t>(address + kWRegSize));
+      DCHECK(access_size == kWRegSize);
+      set_wreg_no_log(rt, MemoryRead<uint32_t>(address));
+      set_wreg_no_log(rt2, MemoryRead<uint32_t>(address2));
       break;
     }
     case LDP_s: {
-      set_sreg(rt, MemoryRead<float>(address));
-      set_sreg(rt2, MemoryRead<float>(address + kSRegSize));
+      DCHECK(access_size == kSRegSize);
+      set_sreg_no_log(rt, MemoryRead<float>(address));
+      set_sreg_no_log(rt2, MemoryRead<float>(address2));
       break;
     }
     case LDP_x: {
-      set_xreg(rt, MemoryRead<uint64_t>(address));
-      set_xreg(rt2, MemoryRead<uint64_t>(address + kXRegSize));
+      DCHECK(access_size == kXRegSize);
+      set_xreg_no_log(rt, MemoryRead<uint64_t>(address));
+      set_xreg_no_log(rt2, MemoryRead<uint64_t>(address2));
       break;
     }
     case LDP_d: {
-      set_dreg(rt, MemoryRead<double>(address));
-      set_dreg(rt2, MemoryRead<double>(address + kDRegSize));
+      DCHECK(access_size == kDRegSize);
+      set_dreg_no_log(rt, MemoryRead<double>(address));
+      set_dreg_no_log(rt2, MemoryRead<double>(address2));
       break;
     }
     case LDPSW_x: {
-      set_xreg(rt, MemoryRead<int32_t>(address));
-      set_xreg(rt2, MemoryRead<int32_t>(address + kWRegSize));
+      DCHECK(access_size == kWRegSize);
+      set_xreg_no_log(rt, MemoryRead<int32_t>(address));
+      set_xreg_no_log(rt2, MemoryRead<int32_t>(address2));
       break;
     }
     case STP_w: {
+      DCHECK(access_size == kWRegSize);
       MemoryWrite<uint32_t>(address, wreg(rt));
-      MemoryWrite<uint32_t>(address + kWRegSize, wreg(rt2));
+      MemoryWrite<uint32_t>(address2, wreg(rt2));
       break;
     }
     case STP_s: {
+      DCHECK(access_size == kSRegSize);
       MemoryWrite<float>(address, sreg(rt));
-      MemoryWrite<float>(address + kSRegSize, sreg(rt2));
+      MemoryWrite<float>(address2, sreg(rt2));
       break;
     }
     case STP_x: {
+      DCHECK(access_size == kXRegSize);
       MemoryWrite<uint64_t>(address, xreg(rt));
-      MemoryWrite<uint64_t>(address + kXRegSize, xreg(rt2));
+      MemoryWrite<uint64_t>(address2, xreg(rt2));
       break;
     }
     case STP_d: {
+      DCHECK(access_size == kDRegSize);
       MemoryWrite<double>(address, dreg(rt));
-      MemoryWrite<double>(address + kDRegSize, dreg(rt2));
+      MemoryWrite<double>(address2, dreg(rt2));
       break;
     }
     default: UNREACHABLE();
   }
 
+  // Print a detailed trace (including the memory address) instead of the basic
+  // register:value trace generated by set_*reg().
+  if (instr->IsLoad()) {
+    if ((op == LDP_s) || (op == LDP_d)) {
+      LogReadFP(address, access_size, rt);
+      LogReadFP(address2, access_size, rt2);
+    } else {
+      LogRead(address, access_size, rt);
+      LogRead(address2, access_size, rt2);
+    }
+  } else {
+    if ((op == STP_s) || (op == STP_d)) {
+      LogWriteFP(address, access_size, rt);
+      LogWriteFP(address2, access_size, rt2);
+    } else {
+      LogWrite(address, access_size, rt);
+      LogWrite(address2, access_size, rt2);
+    }
+  }
+
   // Handle the writeback for loads after the load to ensure safe pop
   // operation even when interrupted in the middle of it. The stack pointer
   // is only updated after the load so pop(fp) will never break the invariant
   // sp <= fp expected while walking the stack in the sampler.
   if (instr->IsLoad()) {
     // For loads the address pre writeback is used to check access below the
     // stack.
-    stack = reinterpret_cast<uint8_t*>(sp());
+    stack = sp();
 
     LoadStoreWriteBack(addr_reg, offset, addrmode);
   }
 
   // Accesses below the stack pointer (but above the platform stack limit) are
   // not allowed in the ABI.
   CheckMemoryAccess(address, stack);
 }
 
 
 void Simulator::VisitLoadLiteral(Instruction* instr) {
-  uint8_t* address = instr->LiteralAddress();
+  uintptr_t address = instr->LiteralAddress();
   unsigned rt = instr->Rt();
 
   switch (instr->Mask(LoadLiteralMask)) {
-    case LDR_w_lit: set_wreg(rt, MemoryRead<uint32_t>(address)); break;
-    case LDR_x_lit: set_xreg(rt, MemoryRead<uint64_t>(address)); break;
-    case LDR_s_lit: set_sreg(rt, MemoryRead<float>(address)); break;
-    case LDR_d_lit: set_dreg(rt, MemoryRead<double>(address)); break;
+    // Use _no_log variants to suppress the register trace (LOG_REGS,
+    // LOG_FP_REGS), then print a more detailed log.
+    case LDR_w_lit:
+      set_wreg_no_log(rt, MemoryRead<uint32_t>(address));
+      LogRead(address, kWRegSize, rt);
+      break;
+    case LDR_x_lit:
+      set_xreg_no_log(rt, MemoryRead<uint64_t>(address));
+      LogRead(address, kXRegSize, rt);
+      break;
+    case LDR_s_lit:
+      set_sreg_no_log(rt, MemoryRead<float>(address));
+      LogReadFP(address, kSRegSize, rt);
+      break;
+    case LDR_d_lit:
+      set_dreg_no_log(rt, MemoryRead<double>(address));
+      LogReadFP(address, kDRegSize, rt);
+      break;
     default: UNREACHABLE();
   }
 }
 
 
-uint8_t* Simulator::LoadStoreAddress(unsigned addr_reg,
-                                     int64_t offset,
-                                     AddrMode addrmode) {
+uintptr_t Simulator::LoadStoreAddress(unsigned addr_reg, int64_t offset,
+                                      AddrMode addrmode) {
   const unsigned kSPRegCode = kSPRegInternalCode & kRegCodeMask;
-  int64_t address = xreg(addr_reg, Reg31IsStackPointer);
+  uint64_t address = xreg(addr_reg, Reg31IsStackPointer);
   if ((addr_reg == kSPRegCode) && ((address % 16) != 0)) {
     // When the base register is SP the stack pointer is required to be
     // quadword aligned prior to the address calculation and write-backs.
     // Misalignment will cause a stack alignment fault.
     FATAL("ALIGNMENT EXCEPTION");
   }
 
   if ((addrmode == Offset) || (addrmode == PreIndex)) {
     address += offset;
   }
 
-  return reinterpret_cast<uint8_t*>(address);
+  return address;
 }
 
 
 void Simulator::LoadStoreWriteBack(unsigned addr_reg,
                                    int64_t offset,
                                    AddrMode addrmode) {
   if ((addrmode == PreIndex) || (addrmode == PostIndex)) {
     DCHECK(offset != 0);
     uint64_t address = xreg(addr_reg, Reg31IsStackPointer);
     set_reg(addr_reg, address + offset, Reg31IsStackPointer);
   }
 }
 
 
-void Simulator::CheckMemoryAccess(uint8_t* address, uint8_t* stack) {
+void Simulator::CheckMemoryAccess(uintptr_t address, uintptr_t stack) {
   if ((address >= stack_limit_) && (address < stack)) {
     fprintf(stream_, "ACCESS BELOW STACK POINTER:\n");
-    fprintf(stream_, "  sp is here:          0x%16p\n", stack);
-    fprintf(stream_, "  access was here:     0x%16p\n", address);
-    fprintf(stream_, "  stack limit is here: 0x%16p\n", stack_limit_);
+    fprintf(stream_, "  sp is here:          0x%016" PRIx64 "\n", stack);
+    fprintf(stream_, "  access was here:     0x%016" PRIx64 "\n", address);
+    fprintf(stream_, "  stack limit is here: 0x%016" PRIx64 "\n", stack_limit_);
     fprintf(stream_, "\n");
     FATAL("ACCESS BELOW STACK POINTER");
   }
 }
 
 
 void Simulator::VisitMoveWideImmediate(Instruction* instr) {
   MoveWideImmediateOp mov_op =
     static_cast<MoveWideImmediateOp>(instr->Mask(MoveWideImmediateMask));
   int64_t new_xn_val = 0;
@@ skipping 534 matching lines @@
     case FCCMP_d: {
       if (ConditionPassed(static_cast<Condition>(instr->Condition()))) {
         // If the condition passes, set the status flags to the result of
         // comparing the operands.
         unsigned reg_size = (instr->Mask(FP64) == FP64) ? kDRegSizeInBits
                                                         : kSRegSizeInBits;
         FPCompare(fpreg(reg_size, instr->Rn()), fpreg(reg_size, instr->Rm()));
       } else {
         // If the condition fails, set the status flags to the nzcv immediate.
         nzcv().SetFlags(instr->Nzcv());
+        LogSystemRegister(NZCV);
       }
       break;
     }
     default: UNIMPLEMENTED();
   }
 }
 
 
 void Simulator::VisitFPConditionalSelect(Instruction* instr) {
   AssertSupportedFPCR();
@@ skipping 762 matching lines @@
       case MRS: {
         switch (instr->ImmSystemRegister()) {
           case NZCV: set_xreg(instr->Rt(), nzcv().RawValue()); break;
           case FPCR: set_xreg(instr->Rt(), fpcr().RawValue()); break;
           default: UNIMPLEMENTED();
         }
         break;
       }
       case MSR: {
         switch (instr->ImmSystemRegister()) {
-          case NZCV: nzcv().SetRawValue(xreg(instr->Rt())); break;
-          case FPCR: fpcr().SetRawValue(xreg(instr->Rt())); break;
+          case NZCV:
+            nzcv().SetRawValue(xreg(instr->Rt()));
+            LogSystemRegister(NZCV);
+            break;
+          case FPCR:
+            fpcr().SetRawValue(xreg(instr->Rt()));
+            LogSystemRegister(FPCR);
+            break;
           default: UNIMPLEMENTED();
         }
         break;
       }
     }
   } else if (instr->Mask(SystemHintFMask) == SystemHintFixed) {
     DCHECK(instr->Mask(SystemHintMask) == HINT);
     switch (instr->ImmHint()) {
       case NOP: break;
       default: UNIMPLEMENTED();
@@ skipping 190 matching lines @@
 
         // Disassemble.
         PrintInstructionsAt(reinterpret_cast<Instruction*>(address),
                             n_of_instrs_to_disasm);
         PrintF("\n");
 
       // print / p -------------------------------------------------------------
       } else if ((strcmp(cmd, "print") == 0) || (strcmp(cmd, "p") == 0)) {
         if (argc == 2) {
           if (strcmp(arg1, "all") == 0) {
-            PrintRegisters(true);
-            PrintFPRegisters(true);
+            PrintRegisters();
+            PrintFPRegisters();
           } else {
             if (!PrintValue(arg1)) {
               PrintF("%s unrecognized\n", arg1);
             }
           }
         } else {
           PrintF(
             "print <register>\n"
             "    Print the content of a register. (alias 'p')\n"
             "    'print all' will print all registers.\n"
@@ skipping 183 matching lines @@
         char const *message =
             reinterpret_cast<char const*>(
                 pc_->InstructionAtOffset(kDebugMessageOffset));
 
         // Always print something when we hit a debug point that breaks.
         // We are going to break, so printing something is not an issue in
         // terms of speed.
         if (FLAG_trace_sim_messages || FLAG_trace_sim || (parameters & BREAK)) {
           if (message != NULL) {
             PrintF(stream_,
-                   "%sDebugger hit %d: %s%s%s\n",
+                   "# %sDebugger hit %d: %s%s%s\n",
                    clr_debug_number,
                    code,
                    clr_debug_message,
                    message,
                    clr_normal);
           } else {
             PrintF(stream_,
-                   "%sDebugger hit %d.%s\n",
+                   "# %sDebugger hit %d.%s\n",
                    clr_debug_number,
                    code,
                    clr_normal);
           }
         }
 
         // Other options.
         switch (parameters & kDebuggerTracingDirectivesMask) {
           case TRACE_ENABLE:
             set_log_parameters(log_parameters() | parameters);
             if (parameters & LOG_SYS_REGS) { PrintSystemRegisters(); }
             if (parameters & LOG_REGS) { PrintRegisters(); }
             if (parameters & LOG_FP_REGS) { PrintFPRegisters(); }
             break;
           case TRACE_DISABLE:
             set_log_parameters(log_parameters() & ~parameters);
             break;
           case TRACE_OVERRIDE:
             set_log_parameters(parameters);
             break;
           default:
             // We don't support a one-shot LOG_DISASM.
             DCHECK((parameters & LOG_DISASM) == 0);
             // Don't print information that is already being traced.
             parameters &= ~log_parameters();
             // Print the requested information.
-            if (parameters & LOG_SYS_REGS) PrintSystemRegisters(true);
-            if (parameters & LOG_REGS) PrintRegisters(true);
-            if (parameters & LOG_FP_REGS) PrintFPRegisters(true);
+            if (parameters & LOG_SYS_REGS) PrintSystemRegisters();
+            if (parameters & LOG_REGS) PrintRegisters();
+            if (parameters & LOG_FP_REGS) PrintFPRegisters();
         }
 
         // The stop parameters are inlined in the code. Skip them:
         //  - Skip to the end of the message string.
         size_t size = kDebugMessageOffset + strlen(message) + 1;
         pc_ = pc_->InstructionAtOffset(RoundUp(size, kInstructionSize));
         //  - Verify that the unreachable marker is present.
         DCHECK(pc_->Mask(ExceptionMask) == HLT);
         DCHECK(pc_->ImmException() ==  kImmExceptionIsUnreachable);
         //  - Skip past the unreachable marker.
@@ skipping 148 matching lines @@
 
   delete[] format;
 }
 
 
 #endif  // USE_SIMULATOR
 
 } }  // namespace v8::internal
 
 #endif  // V8_TARGET_ARCH_ARM64