ARM64: Fix and improve --trace-sim register trace.

ARM64: Fix and improve --trace-sim register trace.

- Use standard names (except that our GREY is the standard BLACK).
- Make non-bold colours explicit, otherwise the boldness can carry over
  into subsequent colour declarations.
- I've moved some colours around to make them consistent. Register value
  updates (which are very common) now stand out less than they did,
  making the less-common (and arguably more important) debug
  announcements appear brighter.
  - FP registers and values are now magenta.
  - Integer registers and values are now cyan.
  - Memory accesses are now blue.
- LOG_WRITE prints the source register for stores.
- Loads are logged with a format similar to that used for stores.
  Specifically, the memory address is printed alongside the new register
  value.
- Updates to D registers print the raw bits as well as the double value.
  Updates to S registers print the raw bits as well as the float value.
  (Previously, we printed both double and float interpretations of the
  bits, which was a bit cluttered.)

BUG=
R=ulan@chromium.org

Committed: https://code.google.com/p/v8/source/detail?r=23732

[jbramley, 2014-09-05 11:22:46]

jacob.bramley@arm.com changed reviewers:
+ bmeurer@chromium.org, ulan@chromium.org

[jbramley, 2014-09-05 11:22:46]

This patch only affects the --trace-sim debug tool. (We use it extensively for
development and debugging.)

Note that I've overridden `git cl format` in a few places where the proposed
format was harder to read. For example, the printf calls become somewhat
confusing if you don't have the line breaks in logical places. Is this Ok?

[ulan, 2014-09-05 11:38:30]

LGTM

> Note that I've overridden `git cl format` in a few places where the proposed
> format was harder to read. For example, the printf calls become somewhat
> confusing if you don't have the line breaks in logical places. Is this Ok?
Yes, since it improves readability.

[jbramley, 2014-09-05 12:10:13]

Committed patchset #2 manually as 23732 (presubmit successful).