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Unified Diff: src/mips/lithium-codegen-mips.cc

Issue 546733003: MIPS: To aid vector-based load ic work, we need to be able to handle the megamorphic load case in h… (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: Created 6 years, 3 months ago
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Index: src/mips/lithium-codegen-mips.cc
diff --git a/src/mips/lithium-codegen-mips.cc b/src/mips/lithium-codegen-mips.cc
index 9a85eca8102dcb97176932c354a637cf9bc6bb48..978ef7324d540cb773a72e356fbc3ce2b03dbc67 100644
--- a/src/mips/lithium-codegen-mips.cc
+++ b/src/mips/lithium-codegen-mips.cc
@@ -30,6 +30,7 @@
#include "src/base/bits.h"
#include "src/code-stubs.h"
#include "src/hydrogen-osr.h"
+#include "src/ic/stub-cache.h"
#include "src/mips/lithium-codegen-mips.h"
#include "src/mips/lithium-gap-resolver-mips.h"
@@ -3934,6 +3935,34 @@ void LCodeGen::DoInvokeFunction(LInvokeFunction* instr) {
}
+void LCodeGen::DoTailCallThroughMegamorphicCache(
+ LTailCallThroughMegamorphicCache* instr) {
+ Register receiver = ToRegister(instr->receiver());
+ Register name = ToRegister(instr->name());
+ DCHECK(receiver.is(LoadDescriptor::ReceiverRegister()));
+ DCHECK(name.is(LoadDescriptor::NameRegister()));
+ DCHECK(receiver.is(a1));
+ DCHECK(name.is(a2));
+
+ Register scratch = a3;
+ Register extra = t0;
+ Register extra2 = t1;
+ Register extra3 = t2;
+
+ // Important for the tail-call.
+ bool must_teardown_frame = NeedsEagerFrame();
+
+ // The probe will tail call to a handler if found.
+ isolate()->stub_cache()->GenerateProbe(masm(), instr->hydrogen()->flags(),
+ must_teardown_frame, receiver, name,
+ scratch, extra, extra2, extra3);
+
+ // Tail call to miss if we ended up here.
+ if (must_teardown_frame) __ LeaveFrame(StackFrame::INTERNAL);
+ LoadIC::GenerateMiss(masm());
+}
+
+
void LCodeGen::DoCallWithDescriptor(LCallWithDescriptor* instr) {
DCHECK(ToRegister(instr->result()).is(v0));
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