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| 1 /* | 1 /* |
| 2 * Copyright (c) 2008-2010 Atheros Communications Inc. | 2 * Copyright (c) 2008-2010 Atheros Communications Inc. |
| 3 * | 3 * |
| 4 * Permission to use, copy, modify, and/or distribute this software for any | 4 * Permission to use, copy, modify, and/or distribute this software for any |
| 5 * purpose with or without fee is hereby granted, provided that the above | 5 * purpose with or without fee is hereby granted, provided that the above |
| 6 * copyright notice and this permission notice appear in all copies. | 6 * copyright notice and this permission notice appear in all copies. |
| 7 * | 7 * |
| 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
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| 154 #define INIT_BCON_CNTRL_REG 0x00000000 | 154 #define INIT_BCON_CNTRL_REG 0x00000000 |
| 155 | 155 |
| 156 #define TU_TO_USEC(_tu) ((_tu) << 10) | 156 #define TU_TO_USEC(_tu) ((_tu) << 10) |
| 157 | 157 |
| 158 #define ATH9K_HW_RX_HP_QDEPTH 16 | 158 #define ATH9K_HW_RX_HP_QDEPTH 16 |
| 159 #define ATH9K_HW_RX_LP_QDEPTH 128 | 159 #define ATH9K_HW_RX_LP_QDEPTH 128 |
| 160 | 160 |
| 161 #define PAPRD_GAIN_TABLE_ENTRIES 32 | 161 #define PAPRD_GAIN_TABLE_ENTRIES 32 |
| 162 #define PAPRD_TABLE_SZ 24 | 162 #define PAPRD_TABLE_SZ 24 |
| 163 | 163 |
| 164 enum ath_hw_txq_subtype { |
| 165 ATH_TXQ_AC_BE = 0, |
| 166 ATH_TXQ_AC_BK = 1, |
| 167 ATH_TXQ_AC_VI = 2, |
| 168 ATH_TXQ_AC_VO = 3, |
| 169 }; |
| 170 |
| 164 enum ath_ini_subsys { | 171 enum ath_ini_subsys { |
| 165 ATH_INI_PRE = 0, | 172 ATH_INI_PRE = 0, |
| 166 ATH_INI_CORE, | 173 ATH_INI_CORE, |
| 167 ATH_INI_POST, | 174 ATH_INI_POST, |
| 168 ATH_INI_NUM_SPLIT, | 175 ATH_INI_NUM_SPLIT, |
| 169 }; | 176 }; |
| 170 | 177 |
| 171 enum wireless_mode { | 178 enum wireless_mode { |
| 172 ATH9K_MODE_11A = 0, | 179 ATH9K_MODE_11A = 0, |
| 173 ATH9K_MODE_11G, | 180 ATH9K_MODE_11G, |
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| 998 #define ATH_PCIE_CAP_LINK_CTRL 0x70 | 1005 #define ATH_PCIE_CAP_LINK_CTRL 0x70 |
| 999 #define ATH_PCIE_CAP_LINK_L0S 1 | 1006 #define ATH_PCIE_CAP_LINK_L0S 1 |
| 1000 #define ATH_PCIE_CAP_LINK_L1 2 | 1007 #define ATH_PCIE_CAP_LINK_L1 2 |
| 1001 | 1008 |
| 1002 #define ATH9K_CLOCK_RATE_CCK 22 | 1009 #define ATH9K_CLOCK_RATE_CCK 22 |
| 1003 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40 | 1010 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40 |
| 1004 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44 | 1011 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44 |
| 1005 #define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM 44 | 1012 #define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM 44 |
| 1006 | 1013 |
| 1007 #endif | 1014 #endif |
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