Update compat-wireless to 2.6.36-5-spn

chromeos/compat-wireless/drivers/net/wireless/ath/ath5k/base.c

 /*-
  * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
  * Copyright (c) 2004-2005 Atheros Communications, Inc.
  * Copyright (c) 2006 Devicescape Software, Inc.
  * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
  * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
  *
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ skipping 30 matching lines @@
  */
 
 #include <linux/module.h>
 #include <linux/delay.h>
 #include <linux/hardirq.h>
 #include <linux/if.h>
 #include <linux/io.h>
 #include <linux/netdevice.h>
 #include <linux/cache.h>
 #include <linux/pci.h>
+#include <linux/pci-aspm.h>
 #include <linux/ethtool.h>
 #include <linux/uaccess.h>
 #include <linux/slab.h>
 
 #include <net/ieee80211_radiotap.h>
 
 #include <asm/unaligned.h>
 
 #include "base.h"
 #include "reg.h"
@@ skipping 444 matching lines @@
 ath5k_pci_probe(struct pci_dev *pdev,
                 const struct pci_device_id *id)
 {
         void __iomem *mem;
         struct ath5k_softc *sc;
         struct ath_common *common;
         struct ieee80211_hw *hw;
         int ret;
         u8 csz;
 
+        /*
+         * L0s needs to be disabled on all ath5k cards.
+         *
+         * For distributions shipping with CONFIG_PCIEASPM (this will be enabled
+         * by default in the future in 2.6.36) this will also mean both L1 and
+         * L0s will be disabled when a pre 1.1 PCIe device is detected. We do
+         * know L1 works correctly even for all ath5k pre 1.1 PCIe devices
+         * though but cannot currently undue the effect of a blacklist, for
+         * details you can read pcie_aspm_sanity_check() and see how it adjusts
+         * the device link capability.
+         *
+         * It may be possible in the future to implement some PCI API to allow
+         * drivers to override blacklists for pre 1.1 PCIe but for now it is
+         * best to accept that both L0s and L1 will be disabled completely for
+         * distributions shipping with CONFIG_PCIEASPM rather than having this
+         * issue present. Motivation for adding this new API will be to help
+         * with power consumption for some of these devices.
+         */
+        pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S);
+
         ret = pci_enable_device(pdev);
         if (ret) {
                 dev_err(&pdev->dev, "can't enable device\n");
                 goto err;
         }
 
         /* XXX 32-bit addressing only */
         ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
         if (ret) {
                 dev_err(&pdev->dev, "32-bit DMA not available\n");
@@ skipping 810 matching lines @@
         u16 duration = 0;
         u8 rc_flags;
 
         flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
 
         /* XXX endianness */
         bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
                         PCI_DMA_TODEVICE);
 
         rate = ieee80211_get_tx_rate(sc->hw, info);
+        if (!rate) {
+                ret = -EINVAL;
+                goto err_unmap;
+        }
 
         if (info->flags & IEEE80211_TX_CTL_NO_ACK)
                 flags |= AR5K_TXDESC_NOACK;
 
         rc_flags = info->control.rates[0].flags;
         hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ?
                 rate->hw_value_short : rate->hw_value;
 
         pktlen = skb->len;
 
@@ skipping 2225 matching lines @@
  * reset.
  */
 static void ath5k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
 {
         struct ath5k_softc *sc = hw->priv;
 
         mutex_lock(&sc->lock);
         ath5k_hw_set_coverage_class(sc->ah, coverage_class);
         mutex_unlock(&sc->lock);
 }