MIPS: First step to cleanup the power-of-2 mess.

src/mips/assembler-mips.cc

 // Copyright (c) 1994-2006 Sun Microsystems Inc.
 // All Rights Reserved.
 //
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 // - Redistributions of source code must retain the above copyright notice,
 // this list of conditions and the following disclaimer.
 //
@@ skipping 19 matching lines @@
 
 // The original source code covered by the above license above has been
 // modified significantly by Google Inc.
 // Copyright 2012 the V8 project authors. All rights reserved.
 
 
 #include "src/v8.h"
 
 #if V8_TARGET_ARCH_MIPS
 
+#include "src/base/bits.h"
 #include "src/base/cpu.h"
 #include "src/mips/assembler-mips-inl.h"
 #include "src/serialize.h"
 
 namespace v8 {
 namespace internal {
 
 // Get the CPU features enabled by the build. For cross compilation the
 // preprocessor symbols CAN_USE_FPU_INSTRUCTIONS
 // can be defined to enable FPU instructions when building the
@@ skipping 282 matching lines @@
   // Set up code descriptor.
   desc->buffer = buffer_;
   desc->buffer_size = buffer_size_;
   desc->instr_size = pc_offset();
   desc->reloc_size = (buffer_ + buffer_size_) - reloc_info_writer.pos();
   desc->origin = this;
 }
 
 
 void Assembler::Align(int m) {
-  DCHECK(m >= 4 && IsPowerOf2(m));
+  DCHECK(m >= 4 && base::bits::IsPowerOfTwo32(m));
   while ((pc_offset() & (m - 1)) != 0) {
     nop();
   }
 }
 
 
 void Assembler::CodeTargetAlign() {
   // No advantage to aligning branch/call targets to more than
   // single instruction, that I am aware of.
   Align(4);
@@ skipping 2385 matching lines @@
 void Assembler::PopulateConstantPool(ConstantPoolArray* constant_pool) {
   // No out-of-line constant pool support.
   DCHECK(!FLAG_enable_ool_constant_pool);
   return;
 }
 
 
 } }  // namespace v8::internal
 
 #endif  // V8_TARGET_ARCH_MIPS