Track live instance and allocation counts for classes

runtime/vm/assembler_ia32.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/globals.h"
 #if defined(TARGET_ARCH_IA32)
 
 #include "vm/assembler.h"
 #include "vm/code_generator.h"
 #include "vm/heap.h"
+#include "vm/heap_class_stats.h"
 #include "vm/memory_region.h"
 #include "vm/runtime_entry.h"
 #include "vm/stack_frame.h"
 #include "vm/stub_code.h"
 
 namespace dart {
 
 DEFINE_FLAG(bool, print_stop_message, true, "Print stop message.");
 DEFINE_FLAG(bool, use_sse41, true, "Use SSE 4.1 if available");
 DECLARE_FLAG(bool, inline_alloc);
@@ skipping 2235 matching lines @@
   while (label->HasNear()) {
     intptr_t position = label->NearPosition();
     intptr_t offset = bound - (position + 1);
     ASSERT(Utils::IsInt(8, offset));
     buffer_.Store<int8_t>(position, offset);
   }
   label->BindTo(bound);
 }
 
 
+// Updates the allocation count for cid.
+void Assembler::BumpAllocationCount(intptr_t cid,
+                                    Register temp_reg) {
+  ASSERT(temp_reg != kNoRegister);
+  HeapClassStatistics* heap_class_stats =
+      Isolate::Current()->heap_class_stats();
+  // temp_reg gets address of class table pointer.
+  movl(temp_reg, Address::Absolute(heap_class_stats->ClassStatsTableAddress()));
+  // Offset into class table.
+  const intptr_t offset = cid * sizeof(HeapClassData);  // NOLINT
+  // temp_reg points at HeapClassData for cid + offset to allocation count.
+  leal(temp_reg, Address(temp_reg, offset));
+  // Increment allocation count.
+  addl(Address(temp_reg, HeapClassData::allocated_since_gc_offset()),
+       Immediate(1));
+}
+
 void Assembler::TryAllocate(const Class& cls,
                             Label* failure,
                             bool near_jump,
                             Register instance_reg) {
   ASSERT(failure != NULL);
   if (FLAG_inline_alloc) {
     Heap* heap = Isolate::Current()->heap();
     const intptr_t instance_size = cls.instance_size();
     movl(instance_reg, Address::Absolute(heap->TopAddress()));
     addl(instance_reg, Immediate(instance_size));
     // instance_reg: potential next object start.
     cmpl(instance_reg, Address::Absolute(heap->EndAddress()));
     j(ABOVE_EQUAL, failure, near_jump);
     // Successfully allocated the object, now update top to point to
     // next object start and store the class in the class field of object.
     movl(Address::Absolute(heap->TopAddress()), instance_reg);
+    pushl(instance_reg);

[Florian Schneider, 2013/10/31 09:56:01]

I suspect that this will make bump allocation a _lot_ slower:
Before: 2 loads, 2 stores.
After:  4 loads, 4 stores.
How will this cost be amortized?

[Cutch, 2013/10/31 11:20:02]

I will run some tests tomorrow against patch set 2 (which uses temp registers).
In some places, like intrinsics, we have registers to use. 

+    BumpAllocationCount(cls.id(), instance_reg);
+    popl(instance_reg);
     ASSERT(instance_size >= kHeapObjectTag);
     subl(instance_reg, Immediate(instance_size - kHeapObjectTag));
     uword tags = 0;
     tags = RawObject::SizeTag::update(instance_size, tags);
     ASSERT(cls.id() != kIllegalCid);
     tags = RawObject::ClassIdTag::update(cls.id(), tags);
     movl(FieldAddress(instance_reg, Object::tags_offset()), Immediate(tags));
   } else {
     jmp(failure);
   }
@@ skipping 215 matching lines @@
 
 const char* Assembler::FpuRegisterName(FpuRegister reg) {
   ASSERT((0 <= reg) && (reg < kNumberOfXmmRegisters));
   return xmm_reg_names[reg];
 }
 
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_IA32