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Issue 51653006: Track live instance and allocation counts for classes (Closed) Base URL: https://dart.googlecode.com/svn/branches/bleeding_edge/dart
Patch Set: Created 6 years, 11 months ago
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1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
2 // for details. All rights reserved. Use of this source code is governed by a 2 // for details. All rights reserved. Use of this source code is governed by a
3 // BSD-style license that can be found in the LICENSE file. 3 // BSD-style license that can be found in the LICENSE file.
4 4
5 #include "vm/globals.h" 5 #include "vm/globals.h"
6 #if defined(TARGET_ARCH_ARM) 6 #if defined(TARGET_ARCH_ARM)
7 7
8 #include "vm/assembler.h" 8 #include "vm/assembler.h"
9 #include "vm/longjump.h" 9 #include "vm/longjump.h"
10 #include "vm/runtime_entry.h" 10 #include "vm/runtime_entry.h"
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2634 } 2634 }
2635 2635
2636 2636
2637 void Assembler::LeaveStubFrame() { 2637 void Assembler::LeaveStubFrame() {
2638 LeaveFrame((1 << PP) | (1 << FP) | (1 << LR)); 2638 LeaveFrame((1 << PP) | (1 << FP) | (1 << LR));
2639 // Adjust SP for null PC pushed in EnterStubFrame. 2639 // Adjust SP for null PC pushed in EnterStubFrame.
2640 AddImmediate(SP, kWordSize); 2640 AddImmediate(SP, kWordSize);
2641 } 2641 }
2642 2642
2643 2643
2644 void Assembler::UpdateAllocationStats(intptr_t cid,
2645 Register temp_reg,
2646 Heap::Space space) {
2647 ASSERT(temp_reg != kNoRegister);
2648 ASSERT(temp_reg != TMP);
2649 ASSERT(cid > 0);
2650 Isolate* isolate = Isolate::Current();
2651 ClassTable* class_table = isolate->class_table();
2652 if (cid < kNumPredefinedCids) {
2653 const uword class_heap_stats_table_address =
2654 class_table->PredefinedClassHeapStatsTableAddress();
2655 const uword class_offset = cid * sizeof(ClassHeapStats); // NOLINT
2656 const uword count_field_offset = (space == Heap::kNew) ?
2657 ClassHeapStats::allocated_since_gc_new_space_offset() :
2658 ClassHeapStats::allocated_since_gc_old_space_offset();
2659 LoadImmediate(temp_reg, class_heap_stats_table_address + class_offset);
2660 const Address& count_address = Address(temp_reg, count_field_offset);
2661 ldr(TMP, count_address);
2662 AddImmediate(TMP, 1);
2663 str(TMP, count_address);
2664 } else {
2665 ASSERT(temp_reg != kNoRegister);
2666 const uword class_offset = cid * sizeof(ClassHeapStats); // NOLINT
2667 const uword count_field_offset = (space == Heap::kNew) ?
2668 ClassHeapStats::allocated_since_gc_new_space_offset() :
2669 ClassHeapStats::allocated_since_gc_old_space_offset();
2670 LoadImmediate(temp_reg, class_table->ClassStatsTableAddress());
2671 ldr(temp_reg, Address(temp_reg, 0));
2672 AddImmediate(temp_reg, class_offset);
2673 ldr(TMP, Address(temp_reg, count_field_offset));
2674 AddImmediate(TMP, 1);
2675 str(TMP, Address(temp_reg, count_field_offset));
2676 }
2677 }
2678
2679
2680 void Assembler::UpdateAllocationStatsWithSize(intptr_t cid,
2681 Register size_reg,
2682 Register temp_reg,
2683 Heap::Space space) {
2684 ASSERT(temp_reg != kNoRegister);
2685 ASSERT(temp_reg != TMP);
2686 ASSERT(cid > 0);
2687 Isolate* isolate = Isolate::Current();
2688 ClassTable* class_table = isolate->class_table();
2689 if (cid < kNumPredefinedCids) {
2690 const uword class_heap_stats_table_address =
2691 class_table->PredefinedClassHeapStatsTableAddress();
2692 const uword class_offset = cid * sizeof(ClassHeapStats); // NOLINT
2693 const uword count_field_offset = (space == Heap::kNew) ?
2694 ClassHeapStats::allocated_since_gc_new_space_offset() :
2695 ClassHeapStats::allocated_since_gc_old_space_offset();
2696 const uword size_field_offset = (space == Heap::kNew) ?
2697 ClassHeapStats::allocated_size_since_gc_new_space_offset() :
2698 ClassHeapStats::allocated_size_since_gc_old_space_offset();
2699 LoadImmediate(temp_reg, class_heap_stats_table_address + class_offset);
2700 const Address& count_address = Address(temp_reg, count_field_offset);
2701 const Address& size_address = Address(temp_reg, size_field_offset);
2702 ldr(TMP, count_address);
2703 AddImmediate(TMP, 1);
2704 str(TMP, count_address);
2705 ldr(TMP, size_address);
2706 add(TMP, TMP, ShifterOperand(size_reg));
2707 str(TMP, size_address);
2708 } else {
2709 ASSERT(temp_reg != kNoRegister);
2710 const uword class_offset = cid * sizeof(ClassHeapStats); // NOLINT
2711 const uword count_field_offset = (space == Heap::kNew) ?
2712 ClassHeapStats::allocated_since_gc_new_space_offset() :
2713 ClassHeapStats::allocated_since_gc_old_space_offset();
2714 const uword size_field_offset = (space == Heap::kNew) ?
2715 ClassHeapStats::allocated_size_since_gc_new_space_offset() :
2716 ClassHeapStats::allocated_size_since_gc_old_space_offset();
2717 LoadImmediate(temp_reg, class_table->ClassStatsTableAddress());
2718 ldr(temp_reg, Address(temp_reg, 0));
2719 AddImmediate(temp_reg, class_offset);
2720 ldr(TMP, Address(temp_reg, count_field_offset));
2721 AddImmediate(TMP, 1);
2722 str(TMP, Address(temp_reg, count_field_offset));
2723 ldr(TMP, Address(temp_reg, size_field_offset));
2724 add(TMP, TMP, ShifterOperand(size_reg));
2725 str(TMP, Address(temp_reg, size_field_offset));
2726 }
2727 }
2728
2729
2644 void Assembler::TryAllocate(const Class& cls, 2730 void Assembler::TryAllocate(const Class& cls,
2645 Label* failure, 2731 Label* failure,
2646 Register instance_reg) { 2732 Register instance_reg,
2733 Register temp_reg) {
2647 ASSERT(failure != NULL); 2734 ASSERT(failure != NULL);
2648 if (FLAG_inline_alloc) { 2735 if (FLAG_inline_alloc) {
2649 Heap* heap = Isolate::Current()->heap(); 2736 Heap* heap = Isolate::Current()->heap();
2650 const intptr_t instance_size = cls.instance_size(); 2737 const intptr_t instance_size = cls.instance_size();
2651 LoadImmediate(instance_reg, heap->TopAddress()); 2738 LoadImmediate(instance_reg, heap->TopAddress());
2652 ldr(instance_reg, Address(instance_reg, 0)); 2739 ldr(instance_reg, Address(instance_reg, 0));
2653 AddImmediate(instance_reg, instance_size); 2740 AddImmediate(instance_reg, instance_size);
2654 2741
2655 // instance_reg: potential next object start. 2742 // instance_reg: potential next object start.
2656 LoadImmediate(IP, heap->EndAddress()); 2743 LoadImmediate(IP, heap->EndAddress());
2657 ldr(IP, Address(IP, 0)); 2744 ldr(IP, Address(IP, 0));
2658 cmp(IP, ShifterOperand(instance_reg)); 2745 cmp(IP, ShifterOperand(instance_reg));
2659 // fail if heap end unsigned less than or equal to instance_reg. 2746 // fail if heap end unsigned less than or equal to instance_reg.
2660 b(failure, LS); 2747 b(failure, LS);
2661 2748
2662 // Successfully allocated the object, now update top to point to 2749 // Successfully allocated the object, now update top to point to
2663 // next object start and store the class in the class field of object. 2750 // next object start and store the class in the class field of object.
2664 LoadImmediate(IP, heap->TopAddress()); 2751 LoadImmediate(IP, heap->TopAddress());
2665 str(instance_reg, Address(IP, 0)); 2752 str(instance_reg, Address(IP, 0));
2666 2753
2667 ASSERT(instance_size >= kHeapObjectTag); 2754 ASSERT(instance_size >= kHeapObjectTag);
2668 AddImmediate(instance_reg, -instance_size + kHeapObjectTag); 2755 AddImmediate(instance_reg, -instance_size + kHeapObjectTag);
2756 UpdateAllocationStats(cls.id(), temp_reg);
2669 2757
2670 uword tags = 0; 2758 uword tags = 0;
2671 tags = RawObject::SizeTag::update(instance_size, tags); 2759 tags = RawObject::SizeTag::update(instance_size, tags);
2672 ASSERT(cls.id() != kIllegalCid); 2760 ASSERT(cls.id() != kIllegalCid);
2673 tags = RawObject::ClassIdTag::update(cls.id(), tags); 2761 tags = RawObject::ClassIdTag::update(cls.id(), tags);
2674 LoadImmediate(IP, tags); 2762 LoadImmediate(IP, tags);
2675 str(IP, FieldAddress(instance_reg, Object::tags_offset())); 2763 str(IP, FieldAddress(instance_reg, Object::tags_offset()));
2676 } else { 2764 } else {
2677 b(failure); 2765 b(failure);
2678 } 2766 }
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2754 2842
2755 2843
2756 const char* Assembler::FpuRegisterName(FpuRegister reg) { 2844 const char* Assembler::FpuRegisterName(FpuRegister reg) {
2757 ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters)); 2845 ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters));
2758 return fpu_reg_names[reg]; 2846 return fpu_reg_names[reg];
2759 } 2847 }
2760 2848
2761 } // namespace dart 2849 } // namespace dart
2762 2850
2763 #endif // defined TARGET_ARCH_ARM 2851 #endif // defined TARGET_ARCH_ARM
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