Generate some intrinsics using our IR.

runtime/vm/constants_arm64.h

Index: runtime/vm/constants_arm64.h
===================================================================
--- runtime/vm/constants_arm64.h	(revision 39651)
+++ runtime/vm/constants_arm64.h	(working copy)
@@ -27,6 +27,7 @@
   R13 = 13,
   R14 = 14,
   R15 = 15,
+  kLastFreeCpuRegister = 15,

[zra, 2014/08/28 17:40:07]

When writing the port, I checked that the allocator always marks IP0, IP1 and
SPREG as unavailable, so I don't think this change is necessary. Instead, I'd
recommend fixing the bug in the parallel move resolver. Otherwise, I believe the
allocator will never be able to use R19-26, which is probably not what we want.

[Florian Schneider, 2014/08/29 10:30:51]

This fix is temporary for now. Ideally, we want to support an arbitrary set of
allocatable registers and not just a continuous range. Right now, there is a lot
of inconsistency. e.g. CTX and PP are inside the range [kFirstFreeCpuRegister,
kLastFreeCpuRegister] on some platforms (x64), and outside that range for others
(ARM64)

Ideally, we want to support an arbitrary set of allocatable registers, and not
just a continuous range. 

   R16 = 16,  // IP0 aka TMP
   R17 = 17,  // IP1 aka TMP2
   R18 = 18,  // SP in Dart code.
@@ -38,7 +39,6 @@
   R24 = 24,
   R25 = 25,
   R26 = 26,
-  kLastFreeCpuRegister = 26,
   R27 = 27,  // PP
   R28 = 28,  // CTX
   R29 = 29,  // FP
@@ -115,6 +115,7 @@
 const Register FPREG = FP;  // Frame pointer register.
 const Register SPREG = R18;  // Stack pointer register.
 const Register ICREG = R5;  // IC data register.
+const Register ARGS_DESC_REG = R4;  // Arguments descriptor register.
 
 // Exception object is passed in this register to the catch handlers when an
 // exception is thrown.