Generate some intrinsics using our IR.

runtime/vm/constants_arm64.h

 // Copyright (c) 2014, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #ifndef VM_CONSTANTS_ARM64_H_
 #define VM_CONSTANTS_ARM64_H_
 
 #include "platform/assert.h"
 
 namespace dart {
 
 enum Register {
   kFirstFreeCpuRegister = 0,
   R0  =  0,
   R1  =  1,
   R2  =  2,
   R3  =  3,
   R4  =  4,
   R5  =  5,
   R6  =  6,
   R7  =  7,
   R8  =  8,
   R9  =  9,
   R10 = 10,
   R11 = 11,
   R12 = 12,
   R13 = 13,
   R14 = 14,
   R15 = 15,
+  kLastFreeCpuRegister = 15,

[zra, 2014/08/28 17:40:07]

When writing the port, I checked that the allocator always marks IP0, IP1 and
SPREG as unavailable, so I don't think this change is necessary. Instead, I'd
recommend fixing the bug in the parallel move resolver. Otherwise, I believe the
allocator will never be able to use R19-26, which is probably not what we want.

[Florian Schneider, 2014/08/29 10:30:51]

This fix is temporary for now. Ideally, we want to support an arbitrary set of
allocatable registers and not just a continuous range. Right now, there is a lot
of inconsistency. e.g. CTX and PP are inside the range [kFirstFreeCpuRegister,
kLastFreeCpuRegister] on some platforms (x64), and outside that range for others
(ARM64)

Ideally, we want to support an arbitrary set of allocatable registers, and not
just a continuous range. 

   R16 = 16,  // IP0 aka TMP
   R17 = 17,  // IP1 aka TMP2
   R18 = 18,  // SP in Dart code.
   R19 = 19,
   R20 = 20,
   R21 = 21,
   R22 = 22,
   R23 = 23,
   R24 = 24,
   R25 = 25,
   R26 = 26,
-  kLastFreeCpuRegister = 26,
   R27 = 27,  // PP
   R28 = 28,  // CTX
   R29 = 29,  // FP
   R30 = 30,  // LR
   R31 = 31,  // ZR, CSP
   kNumberOfCpuRegisters = 32,
   kNoRegister = -1,
 
   // These registers both use the encoding R31, but to avoid mistakes we give
   // them different values, and then translate before encoding.
@@ skipping 56 matching lines @@
 
 // Register aliases.
 const Register TMP = R16;  // Used as scratch register by assembler.
 const Register TMP2 = R17;
 const Register CTX = R28;  // Caches current context in generated code.
 const Register PP = R27;  // Caches object pool pointer in generated code.
 const Register kNoPP = kNoRegister;
 const Register FPREG = FP;  // Frame pointer register.
 const Register SPREG = R18;  // Stack pointer register.
 const Register ICREG = R5;  // IC data register.
+const Register ARGS_DESC_REG = R4;  // Arguments descriptor register.
 
 // Exception object is passed in this register to the catch handlers when an
 // exception is thrown.
 const Register kExceptionObjectReg = R0;
 
 // Stack trace object is passed in this register to the catch handlers when
 // an exception is thrown.
 const Register kStackTraceObjectReg = R1;
 
 // Masks, sizes, etc.
@@ skipping 888 matching lines @@
   static Instr* At(uword pc) { return reinterpret_cast<Instr*>(pc); }
 
  private:
   DISALLOW_ALLOCATION();
   DISALLOW_IMPLICIT_CONSTRUCTORS(Instr);
 };
 
 }  // namespace dart
 
 #endif  // VM_CONSTANTS_ARM64_H_