Generate some intrinsics using our IR.

runtime/vm/flow_graph_allocator.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/flow_graph_allocator.h"
 
 #include "vm/bit_vector.h"
 #include "vm/intermediate_language.h"
 #include "vm/il_printer.h"
 #include "vm/flow_graph.h"
@@ skipping 54 matching lines @@
 static intptr_t ToInstructionStart(intptr_t pos) {
   return (pos & ~1);
 }
 
 
 static intptr_t ToInstructionEnd(intptr_t pos) {
   return (pos | 1);
 }
 
 
-FlowGraphAllocator::FlowGraphAllocator(const FlowGraph& flow_graph)
+FlowGraphAllocator::FlowGraphAllocator(const FlowGraph& flow_graph,
+                                       bool intrinsic_mode)
   : flow_graph_(flow_graph),
     reaching_defs_(flow_graph),
     value_representations_(flow_graph.max_virtual_register_number()),
     block_order_(flow_graph.reverse_postorder()),
     postorder_(flow_graph.postorder()),
     liveness_(flow_graph),
     vreg_count_(flow_graph.max_virtual_register_number()),
     live_ranges_(flow_graph.max_virtual_register_number()),
     cpu_regs_(),
     fpu_regs_(),
     blocked_cpu_registers_(),
     blocked_fpu_registers_(),
     number_of_registers_(0),
     registers_(),
     blocked_registers_(),
-    cpu_spill_slot_count_(0) {
+    cpu_spill_slot_count_(0),
+    intrinsic_mode_(intrinsic_mode) {
   for (intptr_t i = 0; i < vreg_count_; i++) {
     live_ranges_.Add(NULL);
   }
   for (intptr_t i = 0; i < vreg_count_; i++) {
     value_representations_.Add(kNoRepresentation);
   }
 
   // All registers are marked as "not blocked" (array initialized to false).
   // Mark the unavailable ones as "blocked" (true).
   for (intptr_t i = 0; i < kFirstFreeCpuRegister; i++) {
@@ skipping 10 matching lines @@
     blocked_cpu_registers_[TMP2] = true;
   }
   if (PP != kNoRegister) {
     blocked_cpu_registers_[PP] = true;
   }
   blocked_cpu_registers_[SPREG] = true;
   blocked_cpu_registers_[FPREG] = true;
 
   // FpuTMP is used as scratch by optimized code and parallel move resolver.
   blocked_fpu_registers_[FpuTMP] = true;
+
+  // Block additional registers needed preserved when generating intrinsics.
+  // TODO(fschneider): Handle saving and restoring these registers when
+  // generating intrinsic code.
+  if (intrinsic_mode) {
+    blocked_cpu_registers_[ARGS_DESC_REG] = true;
+  }
 }
 
 
 static void DeepLiveness(MaterializeObjectInstr* mat, BitVector* live_in) {
   if (mat->was_visited_for_liveness()) {
     return;
   }
   mat->mark_visited_for_liveness();
 
   for (intptr_t i = 0; i < mat->InputCount(); i++) {
@@ skipping 477 matching lines @@
                                                   LiveRange* range,
                                                   BlockEntryInstr* block) {
   // Save the range end because it may change below.
   intptr_t range_end = range->End();
   if (defn->IsParameter()) {
     ParameterInstr* param = defn->AsParameter();
     // Assert that copied and non-copied parameters are mutually exclusive.
     // This might change in the future and, if so, the index will be wrong.
     ASSERT((flow_graph_.num_copied_params() == 0) ||
            (flow_graph_.num_non_copied_params() == 0));
-    // Slot index for the leftmost copied parameter is 0.
     intptr_t slot_index = param->index();
-    // Slot index for the rightmost fixed parameter is -1.
-    slot_index -= flow_graph_.num_non_copied_params();
+    ASSERT((param->base_reg() == FPREG) || (param->base_reg() == SPREG));
+    if (param->base_reg() == FPREG) {
+      // Slot index for the leftmost copied parameter is 0.
+      // Slot index for the rightmost fixed parameter is -1.
+      slot_index -= flow_graph_.num_non_copied_params();
+    }
 
-    range->set_assigned_location(Location::StackSlot(slot_index));
-    range->set_spill_slot(Location::StackSlot(slot_index));
+    range->set_assigned_location(Location::StackSlot(slot_index,
+                                                     param->base_reg()));
+    range->set_spill_slot(Location::StackSlot(slot_index,
+                                              param->base_reg()));
   } else {
     ConstantInstr* constant = defn->AsConstant();
     ASSERT(constant != NULL);
     range->set_assigned_location(Location::Constant(constant));
     range->set_spill_slot(Location::Constant(constant));
   }
   AssignSafepoints(defn, range);
   range->finger()->Initialize(range);
   UsePosition* use =
       range->finger()->FirstRegisterBeneficialUse(block->start_pos());
@@ skipping 1982 matching lines @@
     const intptr_t start = range->Start();
     TRACE_ALLOC(OS::Print("Processing live range for v%" Pd " "
                           "starting at %" Pd "\n",
                           range->vreg(),
                           start));
 
     // TODO(vegorov): eagerly spill liveranges without register uses.
     AdvanceActiveIntervals(start);
 
     if (!AllocateFreeRegister(range)) {
+      if (intrinsic_mode_) {
+        // No spilling when compiling intrinsics.
+        // TODO(fschneider): Handle spilling in intrinsics. For now, the
+        // IR has to be built so that there are enough free registers.
+        UNREACHABLE();
+      }
       AllocateAnyRegister(range);
     }
   }
 
   // All allocation decisions were done.
   ASSERT(unallocated_.is_empty());
 
   // Finish allocation.
   AdvanceActiveIntervals(kMaxPosition);
   TRACE_ALLOC(OS::Print("Allocation completed\n"));
@@ skipping 282 matching lines @@
     OS::Print("-- [after ssa allocator] ir [%s] -------------\n",
               function.ToFullyQualifiedCString());
     FlowGraphPrinter printer(flow_graph_, true);
     printer.PrintBlocks();
     OS::Print("----------------------------------------------\n");
   }
 }
 
 
 }  // namespace dart