| OLD | NEW |
| 1 ; This is a basic test of the alloca instruction. | 1 ; This is a basic test of the alloca instruction. |
| 2 | 2 |
| 3 ; RUN: %llvm2ice -O2 --verbose none %s | FileCheck %s | |
| 4 ; RUN: %llvm2ice -Om1 --verbose none %s | FileCheck %s | |
| 5 ; RUN: %llvm2ice -O2 --verbose none %s \ | 3 ; RUN: %llvm2ice -O2 --verbose none %s \ |
| 6 ; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj | 4 ; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \ |
| 5 ; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s |
| 7 ; RUN: %llvm2ice -Om1 --verbose none %s \ | 6 ; RUN: %llvm2ice -Om1 --verbose none %s \ |
| 8 ; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj | 7 ; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \ |
| 8 ; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s |
| 9 ; RUN: %llvm2ice --verbose none %s | FileCheck --check-prefix=ERRORS %s | 9 ; RUN: %llvm2ice --verbose none %s | FileCheck --check-prefix=ERRORS %s |
| 10 ; RUN: %llvm2iceinsts %s | %szdiff %s | FileCheck --check-prefix=DUMP %s | 10 ; RUN: %llvm2iceinsts %s | %szdiff %s | FileCheck --check-prefix=DUMP %s |
| 11 ; RUN: %llvm2iceinsts --pnacl %s | %szdiff %s \ | 11 ; RUN: %llvm2iceinsts --pnacl %s | %szdiff %s \ |
| 12 ; RUN: | FileCheck --check-prefix=DUMP %s | 12 ; RUN: | FileCheck --check-prefix=DUMP %s |
| 13 | 13 |
| 14 define void @fixed_416_align_16(i32 %n) { | 14 define void @fixed_416_align_16(i32 %n) { |
| 15 entry: | 15 entry: |
| 16 %array = alloca i8, i32 416, align 16 | 16 %array = alloca i8, i32 416, align 16 |
| 17 %__2 = ptrtoint i8* %array to i32 | 17 %__2 = ptrtoint i8* %array to i32 |
| 18 call void @f1(i32 %__2) | 18 call void @f1(i32 %__2) |
| 19 ret void | 19 ret void |
| 20 } | 20 } |
| 21 ; CHECK-LABEL: fixed_416_align_16: | 21 ; CHECK-LABEL: fixed_416_align_16: |
| 22 ; CHECK: sub esp, 416 | 22 ; CHECK: sub esp, 416 |
| 23 ; CHECK: sub esp, 16 | 23 ; CHECK: sub esp, 16 |
| 24 ; CHECK: mov dword ptr [esp], eax | 24 ; CHECK: mov dword ptr [esp], eax |
| 25 ; CHECK: call f1 | 25 ; CHECK: call f1 |
| 26 | 26 |
| 27 define void @fixed_416_align_32(i32 %n) { | 27 define void @fixed_416_align_32(i32 %n) { |
| 28 entry: | 28 entry: |
| 29 %array = alloca i8, i32 400, align 32 | 29 %array = alloca i8, i32 400, align 32 |
| 30 %__2 = ptrtoint i8* %array to i32 | 30 %__2 = ptrtoint i8* %array to i32 |
| 31 call void @f1(i32 %__2) | 31 call void @f1(i32 %__2) |
| 32 ret void | 32 ret void |
| 33 } | 33 } |
| 34 ; CHECK-LABEL: fixed_416_align_32: | 34 ; CHECK-LABEL: fixed_416_align_32: |
| 35 ; CHECK: and esp, 4294967264 | 35 ; CHECK: and esp, -32 |
| 36 ; CHECK: sub esp, 416 | 36 ; CHECK: sub esp, 416 |
| 37 ; CHECK: sub esp, 16 | 37 ; CHECK: sub esp, 16 |
| 38 ; CHECK: mov dword ptr [esp], eax | 38 ; CHECK: mov dword ptr [esp], eax |
| 39 ; CHECK: call f1 | 39 ; CHECK: call f1 |
| 40 | 40 |
| 41 define void @fixed_351_align_16(i32 %n) { | 41 define void @fixed_351_align_16(i32 %n) { |
| 42 entry: | 42 entry: |
| 43 %array = alloca i8, i32 351, align 16 | 43 %array = alloca i8, i32 351, align 16 |
| 44 %__2 = ptrtoint i8* %array to i32 | 44 %__2 = ptrtoint i8* %array to i32 |
| 45 call void @f1(i32 %__2) | 45 call void @f1(i32 %__2) |
| 46 ret void | 46 ret void |
| 47 } | 47 } |
| 48 ; CHECK-LABEL: fixed_351_align_16: | 48 ; CHECK-LABEL: fixed_351_align_16: |
| 49 ; CHECK: sub esp, 352 | 49 ; CHECK: sub esp, 352 |
| 50 ; CHECK: sub esp, 16 | 50 ; CHECK: sub esp, 16 |
| 51 ; CHECK: mov dword ptr [esp], eax | 51 ; CHECK: mov dword ptr [esp], eax |
| 52 ; CHECK: call f1 | 52 ; CHECK: call f1 |
| 53 | 53 |
| 54 define void @fixed_351_align_32(i32 %n) { | 54 define void @fixed_351_align_32(i32 %n) { |
| 55 entry: | 55 entry: |
| 56 %array = alloca i8, i32 351, align 32 | 56 %array = alloca i8, i32 351, align 32 |
| 57 %__2 = ptrtoint i8* %array to i32 | 57 %__2 = ptrtoint i8* %array to i32 |
| 58 call void @f1(i32 %__2) | 58 call void @f1(i32 %__2) |
| 59 ret void | 59 ret void |
| 60 } | 60 } |
| 61 ; CHECK-LABEL: fixed_351_align_32: | 61 ; CHECK-LABEL: fixed_351_align_32: |
| 62 ; CHECK: and esp, 4294967264 | 62 ; CHECK: and esp, -32 |
| 63 ; CHECK: sub esp, 352 | 63 ; CHECK: sub esp, 352 |
| 64 ; CHECK: sub esp, 16 | 64 ; CHECK: sub esp, 16 |
| 65 ; CHECK: mov dword ptr [esp], eax | 65 ; CHECK: mov dword ptr [esp], eax |
| 66 ; CHECK: call f1 | 66 ; CHECK: call f1 |
| 67 | 67 |
| 68 declare void @f1(i32) | 68 define void @f1(i32 %ignored) { |
| 69 entry: |
| 70 ret void |
| 71 } |
| 69 | 72 |
| 70 define void @variable_n_align_16(i32 %n) { | 73 define void @variable_n_align_16(i32 %n) { |
| 71 entry: | 74 entry: |
| 72 %array = alloca i8, i32 %n, align 16 | 75 %array = alloca i8, i32 %n, align 16 |
| 73 %__2 = ptrtoint i8* %array to i32 | 76 %__2 = ptrtoint i8* %array to i32 |
| 74 call void @f2(i32 %__2) | 77 call void @f2(i32 %__2) |
| 75 ret void | 78 ret void |
| 76 } | 79 } |
| 77 ; CHECK-LABEL: variable_n_align_16: | 80 ; CHECK-LABEL: variable_n_align_16: |
| 78 ; CHECK: mov eax, dword ptr [ebp+8] | 81 ; CHECK: mov eax, dword ptr [ebp + 8] |
| 79 ; CHECK: add eax, 15 | 82 ; CHECK: add eax, 15 |
| 80 ; CHECK: and eax, 4294967280 | 83 ; CHECK: and eax, -16 |
| 81 ; CHECK: sub esp, eax | 84 ; CHECK: sub esp, eax |
| 82 ; CHECK: sub esp, 16 | 85 ; CHECK: sub esp, 16 |
| 83 ; CHECK: mov dword ptr [esp], eax | 86 ; CHECK: mov dword ptr [esp], eax |
| 84 ; CHECK: call f2 | 87 ; CHECK: call f2 |
| 85 | 88 |
| 86 define void @variable_n_align_32(i32 %n) { | 89 define void @variable_n_align_32(i32 %n) { |
| 87 entry: | 90 entry: |
| 88 %array = alloca i8, i32 %n, align 32 | 91 %array = alloca i8, i32 %n, align 32 |
| 89 %__2 = ptrtoint i8* %array to i32 | 92 %__2 = ptrtoint i8* %array to i32 |
| 90 call void @f2(i32 %__2) | 93 call void @f2(i32 %__2) |
| 91 ret void | 94 ret void |
| 92 } | 95 } |
| 93 ; In -O2, the order of the CHECK-DAG lines in the output is switched. | 96 ; In -O2, the order of the CHECK-DAG lines in the output is switched. |
| 94 ; CHECK-LABEL: variable_n_align_32: | 97 ; CHECK-LABEL: variable_n_align_32: |
| 95 ; CHECK-DAG: and esp, 4294967264 | 98 ; CHECK-DAG: and esp, -32 |
| 96 ; CHECK-DAG: mov eax, dword ptr [ebp+8] | 99 ; CHECK-DAG: mov eax, dword ptr [ebp + 8] |
| 97 ; CHECK: add eax, 31 | 100 ; CHECK: add eax, 31 |
| 98 ; CHECK: and eax, 4294967264 | 101 ; CHECK: and eax, -32 |
| 99 ; CHECK: sub esp, eax | 102 ; CHECK: sub esp, eax |
| 100 ; CHECK: sub esp, 16 | 103 ; CHECK: sub esp, 16 |
| 101 ; CHECK: mov dword ptr [esp], eax | 104 ; CHECK: mov dword ptr [esp], eax |
| 102 ; CHECK: call f2 | 105 ; CHECK: call f2 |
| 103 | 106 |
| 104 declare void @f2(i32) | 107 define void @f2(i32 %ignored) { |
| 108 entry: |
| 109 ret void |
| 110 } |
| 105 | 111 |
| 106 ; ERRORS-NOT: ICE translation error | 112 ; ERRORS-NOT: ICE translation error |
| 107 ; DUMP-NOT: SZ | 113 ; DUMP-NOT: SZ |
| OLD | NEW |