OLD | NEW |
---|---|
1 ; This tries to be a comprehensive test of i64 operations, in | 1 ; This tries to be a comprehensive test of i64 operations, in |
2 ; particular the patterns for lowering i64 operations into constituent | 2 ; particular the patterns for lowering i64 operations into constituent |
3 ; i32 operations on x86-32. | 3 ; i32 operations on x86-32. |
4 | 4 |
5 ; RUN: %llvm2ice -O2 --verbose none %s | FileCheck %s | 5 ; TODO(jvoung): remove -ffunction-sections. Sadly... diassembling some |
6 ; RUN: %llvm2ice -Om1 --verbose none %s | FileCheck --check-prefix=OPTM1 %s | 6 ; "ret" within a section are broken in llvm-objdump for LLVM 3.4, and 3.5. |
7 ; It was only fixed in 3.6. | |
jvoung (off chromium)
2014/08/28 17:31:07
Okay, I think the reason such a sad bug existed fo
jvoung (off chromium)
2014/08/29 00:51:20
Done.
| |
8 ; TODO(jvoung): fix extra "CALLTARGETS" run. The llvm-objdump symbolizer | |
9 ; doesn't know how to symbolize non-section-local functions. | |
10 ; The newer LLVM 3.6 one does work, but watch out for other bugs. | |
11 | |
7 ; RUN: %llvm2ice -O2 --verbose none %s \ | 12 ; RUN: %llvm2ice -O2 --verbose none %s \ |
8 ; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj | 13 ; RUN: | FileCheck --check-prefix=CALLTARGETS %s |
9 ; RUN: %llvm2ice -Om1 --verbose none %s \ | 14 ; RUN: %llvm2ice -O2 --verbose none -ffunction-sections %s \ |
10 ; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj | 15 ; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \ |
16 ; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s | |
17 ; RUN: %llvm2ice -Om1 --verbose none -ffunction-sections %s \ | |
18 ; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \ | |
19 ; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - \ | |
20 ; RUN: | FileCheck --check-prefix=OPTM1 %s | |
11 ; RUN: %llvm2ice --verbose none %s | FileCheck --check-prefix=ERRORS %s | 21 ; RUN: %llvm2ice --verbose none %s | FileCheck --check-prefix=ERRORS %s |
12 ; RUN: %llvm2iceinsts %s | %szdiff %s | FileCheck --check-prefix=DUMP %s | 22 ; RUN: %llvm2iceinsts %s | %szdiff %s | FileCheck --check-prefix=DUMP %s |
13 ; RUN: %llvm2iceinsts --pnacl %s | %szdiff %s \ | 23 ; RUN: %llvm2iceinsts --pnacl %s | %szdiff %s \ |
14 ; RUN: | FileCheck --check-prefix=DUMP %s | 24 ; RUN: | FileCheck --check-prefix=DUMP %s |
15 | 25 |
16 @__init_array_start = internal constant [0 x i8] zeroinitializer, align 4 | 26 @__init_array_start = internal constant [0 x i8] zeroinitializer, align 4 |
17 @__fini_array_start = internal constant [0 x i8] zeroinitializer, align 4 | 27 @__fini_array_start = internal constant [0 x i8] zeroinitializer, align 4 |
18 @__tls_template_start = internal constant [0 x i8] zeroinitializer, align 8 | 28 @__tls_template_start = internal constant [0 x i8] zeroinitializer, align 8 |
19 @__tls_template_alignment = internal constant [4 x i8] c"\01\00\00\00", align 4 | 29 @__tls_template_alignment = internal constant [4 x i8] c"\01\00\00\00", align 4 |
20 | 30 |
21 define internal i32 @ignore64BitArg(i64 %a, i32 %b, i64 %c) { | 31 define internal i32 @ignore64BitArg(i64 %a, i32 %b, i64 %c) { |
22 entry: | 32 entry: |
23 ret i32 %b | 33 ret i32 %b |
24 } | 34 } |
25 | 35 |
26 define internal i32 @pass64BitArg(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e, i64 %f ) { | 36 define internal i32 @pass64BitArg(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e, i64 %f ) { |
27 entry: | 37 entry: |
28 %call = call i32 @ignore64BitArgNoInline(i64 %a, i32 123, i64 %b) | 38 %call = call i32 @ignore64BitArgNoInline(i64 %a, i32 123, i64 %b) |
29 %call1 = call i32 @ignore64BitArgNoInline(i64 %c, i32 123, i64 %d) | 39 %call1 = call i32 @ignore64BitArgNoInline(i64 %c, i32 123, i64 %d) |
30 %call2 = call i32 @ignore64BitArgNoInline(i64 %e, i32 123, i64 %f) | 40 %call2 = call i32 @ignore64BitArgNoInline(i64 %e, i32 123, i64 %f) |
31 %add = add i32 %call1, %call | 41 %add = add i32 %call1, %call |
32 %add3 = add i32 %add, %call2 | 42 %add3 = add i32 %add, %call2 |
33 ret i32 %add3 | 43 ret i32 %add3 |
34 } | 44 } |
35 ; CHECK-LABEL: pass64BitArg | 45 ; CHECK-LABEL: pass64BitArg |
36 ; CHECK: sub esp | 46 ; CHECK: sub esp |
37 ; CHECK: mov dword ptr [esp+4] | 47 ; CHECK: mov dword ptr [esp + 4] |
38 ; CHECK: mov dword ptr [esp] | 48 ; CHECK: mov dword ptr [esp] |
39 ; CHECK: mov dword ptr [esp+8], 123 | 49 ; CHECK: mov dword ptr [esp + 8], 123 |
40 ; CHECK: mov dword ptr [esp+16] | 50 ; CHECK: mov dword ptr [esp + 16] |
41 ; CHECK: mov dword ptr [esp+12] | 51 ; CHECK: mov dword ptr [esp + 12] |
42 ; CHECK: call ignore64BitArgNoInline | 52 ; CHECK: call -4 |
43 ; CHECK sub esp | 53 ; CALLTARGETS-LABEL: pass64BitArg |
Jim Stichnoth
2014/08/28 20:19:23
Even though this line was wrong ("CHECK" instead o
jvoung (off chromium)
2014/08/29 00:51:20
Oops, must have accidentally overwritten it with t
|
Jim Stichnoth
2014/08/28 20:19:23
Would it be clearer to move this -LABEL up with th
jvoung (off chromium)
2014/08/29 00:51:20
Done.
Jim Stichnoth
2014/08/29 16:40:49
Thanks. I should have said that this comment appl
jvoung (off chromium)
2014/08/29 19:27:48
Done.
|
44 ; CHECK: mov dword ptr [esp+4] | 54 ; CALLTARGETS: call ignore64BitArgNoInline |
55 ; CHECK: mov dword ptr [esp + 4] | |
45 ; CHECK: mov dword ptr [esp] | 56 ; CHECK: mov dword ptr [esp] |
46 ; CHECK: mov dword ptr [esp+8], 123 | 57 ; CHECK: mov dword ptr [esp + 8], 123 |
47 ; CHECK: mov dword ptr [esp+16] | 58 ; CHECK: mov dword ptr [esp + 16] |
48 ; CHECK: mov dword ptr [esp+12] | 59 ; CHECK: mov dword ptr [esp + 12] |
49 ; CHECK: call ignore64BitArgNoInline | 60 ; CHECK: call -4 |
61 ; CALLTARGETS: call ignore64BitArgNoInline | |
50 ; CHECK: sub esp | 62 ; CHECK: sub esp |
51 ; CHECK: mov dword ptr [esp+4] | 63 ; CHECK: mov dword ptr [esp + 4] |
52 ; CHECK: mov dword ptr [esp] | 64 ; CHECK: mov dword ptr [esp] |
53 ; CHECK: mov dword ptr [esp+8], 123 | 65 ; CHECK: mov dword ptr [esp + 8], 123 |
54 ; CHECK: mov dword ptr [esp+16] | 66 ; CHECK: mov dword ptr [esp + 16] |
55 ; CHECK: mov dword ptr [esp+12] | 67 ; CHECK: mov dword ptr [esp + 12] |
56 ; CHECK: call ignore64BitArgNoInline | 68 ; CHECK: call -4 |
69 ; CALLTARGETS: call ignore64BitArgNoInline | |
57 ; | 70 ; |
58 ; OPTM1-LABEL: pass64BitArg | 71 ; OPTM1-LABEL: pass64BitArg |
59 ; OPTM1: sub esp | 72 ; OPTM1: sub esp |
60 ; OPTM1: mov dword ptr [esp+4] | 73 ; OPTM1: mov dword ptr [esp + 4] |
61 ; OPTM1: mov dword ptr [esp] | 74 ; OPTM1: mov dword ptr [esp] |
62 ; OPTM1: mov dword ptr [esp+8], 123 | 75 ; OPTM1: mov dword ptr [esp + 8], 123 |
63 ; OPTM1: mov dword ptr [esp+16] | 76 ; OPTM1: mov dword ptr [esp + 16] |
64 ; OPTM1: mov dword ptr [esp+12] | 77 ; OPTM1: mov dword ptr [esp + 12] |
65 ; OPTM1: call ignore64BitArgNoInline | 78 ; OPTM1: call -4 |
66 ; OPTM1 sub esp | 79 ; OPTM1: sub esp |
67 ; OPTM1: mov dword ptr [esp+4] | 80 ; OPTM1: mov dword ptr [esp + 4] |
68 ; OPTM1: mov dword ptr [esp] | 81 ; OPTM1: mov dword ptr [esp] |
69 ; OPTM1: mov dword ptr [esp+8], 123 | 82 ; OPTM1: mov dword ptr [esp + 8], 123 |
70 ; OPTM1: mov dword ptr [esp+16] | 83 ; OPTM1: mov dword ptr [esp + 16] |
71 ; OPTM1: mov dword ptr [esp+12] | 84 ; OPTM1: mov dword ptr [esp + 12] |
72 ; OPTM1: call ignore64BitArgNoInline | 85 ; OPTM1: call -4 |
73 ; OPTM1: sub esp | 86 ; OPTM1: sub esp |
74 ; OPTM1: mov dword ptr [esp+4] | 87 ; OPTM1: mov dword ptr [esp + 4] |
75 ; OPTM1: mov dword ptr [esp] | 88 ; OPTM1: mov dword ptr [esp] |
76 ; OPTM1: mov dword ptr [esp+8], 123 | 89 ; OPTM1: mov dword ptr [esp + 8], 123 |
77 ; OPTM1: mov dword ptr [esp+16] | 90 ; OPTM1: mov dword ptr [esp + 16] |
78 ; OPTM1: mov dword ptr [esp+12] | 91 ; OPTM1: mov dword ptr [esp + 12] |
79 ; OPTM1: call ignore64BitArgNoInline | 92 ; OPTM1: call -4 |
80 | 93 |
81 declare i32 @ignore64BitArgNoInline(i64, i32, i64) | 94 declare i32 @ignore64BitArgNoInline(i64, i32, i64) |
82 | 95 |
83 define internal i32 @pass64BitConstArg(i64 %a, i64 %b) { | 96 define internal i32 @pass64BitConstArg(i64 %a, i64 %b) { |
84 entry: | 97 entry: |
85 %call = call i32 @ignore64BitArgNoInline(i64 %a, i32 123, i64 -240105309230672 5256) | 98 %call = call i32 @ignore64BitArgNoInline(i64 %a, i32 123, i64 -240105309230672 5256) |
86 ret i32 %call | 99 ret i32 %call |
87 } | 100 } |
88 ; CHECK-LABEL: pass64BitConstArg | 101 ; CHECK-LABEL: pass64BitConstArg |
89 ; CHECK: sub esp | 102 ; CHECK: sub esp |
90 ; CHECK: mov dword ptr [esp+4] | 103 ; CHECK: mov dword ptr [esp + 4] |
91 ; CHECK-NEXT: mov dword ptr [esp] | 104 ; CHECK-NEXT: mov dword ptr [esp] |
92 ; CHECK-NEXT: mov dword ptr [esp+8], 123 | 105 ; CHECK-NEXT: mov dword ptr [esp + 8], 123 |
93 ; CHECK-NEXT: mov dword ptr [esp+16], 3735928559 | 106 ; Bundle padding added by -triple=i686-none-nacl. |
Jim Stichnoth
2014/08/28 20:19:23
It would be nice if there were a way to match "zer
jvoung (off chromium)
2014/08/29 00:51:20
Acknowledged. Not sure how either =(
| |
94 ; CHECK-NEXT: mov dword ptr [esp+12], 305419896 | 107 ; CHECK-NEXT: nop |
95 ; CHECK-NEXT: call ignore64BitArgNoInline | 108 ; CHECK-NEXT: mov dword ptr [esp + 16], 3735928559 |
109 ; CHECK-NEXT: mov dword ptr [esp + 12], 305419896 | |
110 ; CHECK-NEXT: call -4 | |
111 ; CALLTARGETS-LABEL: pass64BitConstArg | |
112 ; CALLTARGETS: call ignore64BitArgNoInline | |
96 ; | 113 ; |
97 ; OPTM1-LABEL: pass64BitConstArg | 114 ; OPTM1-LABEL: pass64BitConstArg |
98 ; OPTM1: sub esp | 115 ; OPTM1: sub esp |
99 ; OPTM1: mov dword ptr [esp+4] | 116 ; OPTM1: mov dword ptr [esp + 4] |
100 ; OPTM1-NEXT: mov dword ptr [esp] | 117 ; OPTM1-NEXT: mov dword ptr [esp] |
101 ; OPTM1-NEXT: mov dword ptr [esp+8], 123 | 118 ; OPTM1-NEXT: mov dword ptr [esp + 8], 123 |
102 ; OPTM1-NEXT: mov dword ptr [esp+16], 3735928559 | 119 ; Bundle padding added by -triple=i686-none-nacl. |
103 ; OPTM1-NEXT: mov dword ptr [esp+12], 305419896 | 120 ; OPTM1-NEXT: nop |
104 ; OPTM1-NEXT: call ignore64BitArgNoInline | 121 ; OPTM1-NEXT: mov dword ptr [esp + 16], 3735928559 |
122 ; OPTM1-NEXT: mov dword ptr [esp + 12], 305419896 | |
123 ; OPTM1-NEXT: call -4 | |
105 | 124 |
106 define internal i64 @return64BitArg(i64 %a) { | 125 define internal i64 @return64BitArg(i64 %a) { |
107 entry: | 126 entry: |
108 ret i64 %a | 127 ret i64 %a |
109 } | 128 } |
110 ; CHECK-LABEL: return64BitArg | 129 ; CHECK-LABEL: return64BitArg |
111 ; CHECK: mov {{.*}}, dword ptr [esp+4] | 130 ; CHECK: mov {{.*}}, dword ptr [esp + 4] |
112 ; CHECK: mov {{.*}}, dword ptr [esp+8] | 131 ; CHECK: mov {{.*}}, dword ptr [esp + 8] |
113 ; CHECK: ret | 132 ; CHECK: ret |
114 ; | 133 ; |
115 ; OPTM1-LABEL: return64BitArg | 134 ; OPTM1-LABEL: return64BitArg |
116 ; OPTM1: mov {{.*}}, dword ptr [esp+4] | 135 ; OPTM1: mov {{.*}}, dword ptr [esp + 4] |
117 ; OPTM1: mov {{.*}}, dword ptr [esp+8] | 136 ; OPTM1: mov {{.*}}, dword ptr [esp + 8] |
118 ; OPTM1: ret | 137 ; OPTM1: ret |
119 | 138 |
120 define internal i64 @return64BitConst() { | 139 define internal i64 @return64BitConst() { |
121 entry: | 140 entry: |
122 ret i64 -2401053092306725256 | 141 ret i64 -2401053092306725256 |
123 } | 142 } |
124 ; CHECK-LABEL: return64BitConst | 143 ; CHECK-LABEL: return64BitConst |
125 ; CHECK: mov eax, 305419896 | 144 ; CHECK: mov eax, 305419896 |
126 ; CHECK: mov edx, 3735928559 | 145 ; CHECK: mov edx, 3735928559 |
127 ; CHECK: ret | 146 ; CHECK: ret |
(...skipping 104 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... | |
232 ; OPTM1: add | 251 ; OPTM1: add |
233 ; OPTM1: add | 252 ; OPTM1: add |
234 ; OPTM1: ret | 253 ; OPTM1: ret |
235 | 254 |
236 define internal i64 @div64BitSigned(i64 %a, i64 %b) { | 255 define internal i64 @div64BitSigned(i64 %a, i64 %b) { |
237 entry: | 256 entry: |
238 %div = sdiv i64 %a, %b | 257 %div = sdiv i64 %a, %b |
239 ret i64 %div | 258 ret i64 %div |
240 } | 259 } |
241 ; CHECK-LABEL: div64BitSigned | 260 ; CHECK-LABEL: div64BitSigned |
242 ; CHECK: call __divdi3 | 261 ; CHECK: call -4 |
243 ; CHECK: ret | 262 ; CHECK: ret |
263 ; CALLTARGETS-LABEL: div64BitSigned | |
264 ; CALLTARGETS: call __divdi3 | |
244 ; | 265 ; |
245 ; OPTM1-LABEL: div64BitSigned | 266 ; OPTM1-LABEL: div64BitSigned |
246 ; OPTM1: call __divdi3 | 267 ; OPTM1: call -4 |
247 ; OPTM1: ret | 268 ; OPTM1: ret |
248 | 269 |
249 define internal i64 @div64BitSignedConst(i64 %a) { | 270 define internal i64 @div64BitSignedConst(i64 %a) { |
250 entry: | 271 entry: |
251 %div = sdiv i64 %a, 12345678901234 | 272 %div = sdiv i64 %a, 12345678901234 |
252 ret i64 %div | 273 ret i64 %div |
253 } | 274 } |
254 ; CHECK-LABEL: div64BitSignedConst | 275 ; CHECK-LABEL: div64BitSignedConst |
255 ; CHECK: mov dword ptr [esp+12], 2874 | 276 ; CHECK: mov dword ptr [esp + 12], 2874 |
256 ; CHECK: mov dword ptr [esp+8], 1942892530 | 277 ; CHECK: mov dword ptr [esp + 8], 1942892530 |
257 ; CHECK: call __divdi3 | 278 ; CHECK: call -4 |
258 ; CHECK: ret | 279 ; CHECK: ret |
280 ; CALLTARGETS-LABEL: div64BitSignedConst | |
281 ; CALLTARGETS: call __divdi3 | |
259 ; | 282 ; |
260 ; OPTM1-LABEL: div64BitSignedConst | 283 ; OPTM1-LABEL: div64BitSignedConst |
261 ; OPTM1: mov dword ptr [esp+12], 2874 | 284 ; OPTM1: mov dword ptr [esp + 12], 2874 |
262 ; OPTM1: mov dword ptr [esp+8], 1942892530 | 285 ; OPTM1: mov dword ptr [esp + 8], 1942892530 |
263 ; OPTM1: call __divdi3 | 286 ; OPTM1: call -4 |
264 ; OPTM1: ret | 287 ; OPTM1: ret |
265 | 288 |
266 define internal i64 @div64BitUnsigned(i64 %a, i64 %b) { | 289 define internal i64 @div64BitUnsigned(i64 %a, i64 %b) { |
267 entry: | 290 entry: |
268 %div = udiv i64 %a, %b | 291 %div = udiv i64 %a, %b |
269 ret i64 %div | 292 ret i64 %div |
270 } | 293 } |
271 ; CHECK-LABEL: div64BitUnsigned | 294 ; CHECK-LABEL: div64BitUnsigned |
272 ; CHECK: call __udivdi3 | 295 ; CHECK: call -4 |
273 ; CHECK: ret | 296 ; CHECK: ret |
297 ; CALLTARGETS-LABEL: div64BitUnsigned | |
298 ; CALLTARGETS: call __udivdi3 | |
274 ; | 299 ; |
275 ; OPTM1-LABEL: div64BitUnsigned | 300 ; OPTM1-LABEL: div64BitUnsigned |
276 ; OPTM1: call __udivdi3 | 301 ; OPTM1: call -4 |
277 ; OPTM1: ret | 302 ; OPTM1: ret |
278 | 303 |
279 define internal i64 @rem64BitSigned(i64 %a, i64 %b) { | 304 define internal i64 @rem64BitSigned(i64 %a, i64 %b) { |
280 entry: | 305 entry: |
281 %rem = srem i64 %a, %b | 306 %rem = srem i64 %a, %b |
282 ret i64 %rem | 307 ret i64 %rem |
283 } | 308 } |
284 ; CHECK-LABEL: rem64BitSigned | 309 ; CHECK-LABEL: rem64BitSigned |
285 ; CHECK: call __moddi3 | 310 ; CHECK: call -4 |
286 ; CHECK: ret | 311 ; CHECK: ret |
312 ; CALLTARGETS-LABEL: rem64BitSigned | |
313 ; CALLTARGETS: call __moddi3 | |
287 ; | 314 ; |
288 ; OPTM1-LABEL: rem64BitSigned | 315 ; OPTM1-LABEL: rem64BitSigned |
289 ; OPTM1: call __moddi3 | 316 ; OPTM1: call -4 |
290 ; OPTM1: ret | 317 ; OPTM1: ret |
291 | 318 |
292 define internal i64 @rem64BitUnsigned(i64 %a, i64 %b) { | 319 define internal i64 @rem64BitUnsigned(i64 %a, i64 %b) { |
293 entry: | 320 entry: |
294 %rem = urem i64 %a, %b | 321 %rem = urem i64 %a, %b |
295 ret i64 %rem | 322 ret i64 %rem |
296 } | 323 } |
297 ; CHECK-LABEL: rem64BitUnsigned | 324 ; CHECK-LABEL: rem64BitUnsigned |
298 ; CHECK: call __umoddi3 | 325 ; CHECK: call -4 |
299 ; CHECK: ret | 326 ; CHECK: ret |
327 ; CALLTARGETS-LABEL: rem64BitUnsigned | |
328 ; CALLTARGETS: call __umoddi3 | |
300 ; | 329 ; |
301 ; OPTM1-LABEL: rem64BitUnsigned | 330 ; OPTM1-LABEL: rem64BitUnsigned |
302 ; OPTM1: call __umoddi3 | 331 ; OPTM1: call -4 |
303 ; OPTM1: ret | 332 ; OPTM1: ret |
304 | 333 |
305 define internal i64 @shl64BitSigned(i64 %a, i64 %b) { | 334 define internal i64 @shl64BitSigned(i64 %a, i64 %b) { |
306 entry: | 335 entry: |
307 %shl = shl i64 %a, %b | 336 %shl = shl i64 %a, %b |
308 ret i64 %shl | 337 ret i64 %shl |
309 } | 338 } |
310 ; CHECK-LABEL: shl64BitSigned | 339 ; CHECK-LABEL: shl64BitSigned |
311 ; CHECK: shld | 340 ; CHECK: shld |
312 ; CHECK: shl e | 341 ; CHECK: shl e |
(...skipping 136 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... | |
449 ; OPTM1-LABEL: xor64BitUnsigned | 478 ; OPTM1-LABEL: xor64BitUnsigned |
450 ; OPTM1: xor | 479 ; OPTM1: xor |
451 ; OPTM1: xor | 480 ; OPTM1: xor |
452 | 481 |
453 define internal i32 @trunc64To32Signed(i64 %a) { | 482 define internal i32 @trunc64To32Signed(i64 %a) { |
454 entry: | 483 entry: |
455 %conv = trunc i64 %a to i32 | 484 %conv = trunc i64 %a to i32 |
456 ret i32 %conv | 485 ret i32 %conv |
457 } | 486 } |
458 ; CHECK-LABEL: trunc64To32Signed | 487 ; CHECK-LABEL: trunc64To32Signed |
459 ; CHECK: mov eax, dword ptr [esp+4] | 488 ; CHECK: mov eax, dword ptr [esp + 4] |
460 ; CHECK-NEXT: ret | 489 ; CHECK-NEXT: ret |
461 ; | 490 ; |
462 ; OPTM1-LABEL: trunc64To32Signed | 491 ; OPTM1-LABEL: trunc64To32Signed |
463 ; OPTM1: mov eax, dword ptr [esp+ | 492 ; OPTM1: mov eax, dword ptr [esp + |
464 ; OPTM1: ret | 493 ; OPTM1: ret |
465 | 494 |
466 define internal i32 @trunc64To16Signed(i64 %a) { | 495 define internal i32 @trunc64To16Signed(i64 %a) { |
467 entry: | 496 entry: |
468 %conv = trunc i64 %a to i16 | 497 %conv = trunc i64 %a to i16 |
469 %conv.ret_ext = sext i16 %conv to i32 | 498 %conv.ret_ext = sext i16 %conv to i32 |
470 ret i32 %conv.ret_ext | 499 ret i32 %conv.ret_ext |
471 } | 500 } |
472 ; CHECK-LABEL: trunc64To16Signed | 501 ; CHECK-LABEL: trunc64To16Signed |
473 ; CHECK: mov eax, dword ptr [esp+4] | 502 ; CHECK: mov eax, dword ptr [esp + 4] |
474 ; CHECK-NEXT: movsx eax, ax | 503 ; CHECK-NEXT: movsx eax, ax |
475 ; CHECK-NEXT: ret | 504 ; CHECK-NEXT: ret |
476 ; | 505 ; |
477 ; OPTM1-LABEL: trunc64To16Signed | 506 ; OPTM1-LABEL: trunc64To16Signed |
478 ; OPTM1: mov eax, dword ptr [esp+ | 507 ; OPTM1: mov eax, dword ptr [esp + |
479 ; OPTM1: movsx eax, | 508 ; OPTM1: movsx eax, |
480 ; OPTM1: ret | 509 ; OPTM1: ret |
481 | 510 |
482 define internal i32 @trunc64To8Signed(i64 %a) { | 511 define internal i32 @trunc64To8Signed(i64 %a) { |
483 entry: | 512 entry: |
484 %conv = trunc i64 %a to i8 | 513 %conv = trunc i64 %a to i8 |
485 %conv.ret_ext = sext i8 %conv to i32 | 514 %conv.ret_ext = sext i8 %conv to i32 |
486 ret i32 %conv.ret_ext | 515 ret i32 %conv.ret_ext |
487 } | 516 } |
488 ; CHECK-LABEL: trunc64To8Signed | 517 ; CHECK-LABEL: trunc64To8Signed |
489 ; CHECK: mov eax, dword ptr [esp+4] | 518 ; CHECK: mov eax, dword ptr [esp + 4] |
490 ; CHECK-NEXT: movsx eax, al | 519 ; CHECK-NEXT: movsx eax, al |
491 ; CHECK-NEXT: ret | 520 ; CHECK-NEXT: ret |
492 ; | 521 ; |
493 ; OPTM1-LABEL: trunc64To8Signed | 522 ; OPTM1-LABEL: trunc64To8Signed |
494 ; OPTM1: mov eax, dword ptr [esp+ | 523 ; OPTM1: mov eax, dword ptr [esp + |
495 ; OPTM1: movsx eax, | 524 ; OPTM1: movsx eax, |
496 ; OPTM1: ret | 525 ; OPTM1: ret |
497 | 526 |
498 define internal i32 @trunc64To32SignedConst() { | 527 define internal i32 @trunc64To32SignedConst() { |
499 entry: | 528 entry: |
500 %conv = trunc i64 12345678901234 to i32 | 529 %conv = trunc i64 12345678901234 to i32 |
501 ret i32 %conv | 530 ret i32 %conv |
502 } | 531 } |
503 ; CHECK-LABEL: trunc64To32SignedConst | 532 ; CHECK-LABEL: trunc64To32SignedConst |
504 ; CHECK: mov eax, 1942892530 | 533 ; CHECK: mov eax, 1942892530 |
(...skipping 14 matching lines...) Expand all Loading... | |
519 ; OPTM1-LABEL: trunc64To16SignedConst | 548 ; OPTM1-LABEL: trunc64To16SignedConst |
520 ; OPTM1: mov eax, 1942892530 | 549 ; OPTM1: mov eax, 1942892530 |
521 ; OPTM1: movsx eax, | 550 ; OPTM1: movsx eax, |
522 | 551 |
523 define internal i32 @trunc64To32Unsigned(i64 %a) { | 552 define internal i32 @trunc64To32Unsigned(i64 %a) { |
524 entry: | 553 entry: |
525 %conv = trunc i64 %a to i32 | 554 %conv = trunc i64 %a to i32 |
526 ret i32 %conv | 555 ret i32 %conv |
527 } | 556 } |
528 ; CHECK-LABEL: trunc64To32Unsigned | 557 ; CHECK-LABEL: trunc64To32Unsigned |
529 ; CHECK: mov eax, dword ptr [esp+4] | 558 ; CHECK: mov eax, dword ptr [esp + 4] |
530 ; CHECK-NEXT: ret | 559 ; CHECK-NEXT: ret |
531 ; | 560 ; |
532 ; OPTM1-LABEL: trunc64To32Unsigned | 561 ; OPTM1-LABEL: trunc64To32Unsigned |
533 ; OPTM1: mov eax, dword ptr [esp+ | 562 ; OPTM1: mov eax, dword ptr [esp + |
534 ; OPTM1: ret | 563 ; OPTM1: ret |
535 | 564 |
536 define internal i32 @trunc64To16Unsigned(i64 %a) { | 565 define internal i32 @trunc64To16Unsigned(i64 %a) { |
537 entry: | 566 entry: |
538 %conv = trunc i64 %a to i16 | 567 %conv = trunc i64 %a to i16 |
539 %conv.ret_ext = zext i16 %conv to i32 | 568 %conv.ret_ext = zext i16 %conv to i32 |
540 ret i32 %conv.ret_ext | 569 ret i32 %conv.ret_ext |
541 } | 570 } |
542 ; CHECK-LABEL: trunc64To16Unsigned | 571 ; CHECK-LABEL: trunc64To16Unsigned |
543 ; CHECK: mov eax, dword ptr [esp+4] | 572 ; CHECK: mov eax, dword ptr [esp + 4] |
544 ; CHECK-NEXT: movzx eax, ax | 573 ; CHECK-NEXT: movzx eax, ax |
545 ; CHECK-NEXT: ret | 574 ; CHECK-NEXT: ret |
546 ; | 575 ; |
547 ; OPTM1-LABEL: trunc64To16Unsigned | 576 ; OPTM1-LABEL: trunc64To16Unsigned |
548 ; OPTM1: mov eax, dword ptr [esp+ | 577 ; OPTM1: mov eax, dword ptr [esp + |
549 ; OPTM1: movzx eax, | 578 ; OPTM1: movzx eax, |
550 ; OPTM1: ret | 579 ; OPTM1: ret |
551 | 580 |
552 define internal i32 @trunc64To8Unsigned(i64 %a) { | 581 define internal i32 @trunc64To8Unsigned(i64 %a) { |
553 entry: | 582 entry: |
554 %conv = trunc i64 %a to i8 | 583 %conv = trunc i64 %a to i8 |
555 %conv.ret_ext = zext i8 %conv to i32 | 584 %conv.ret_ext = zext i8 %conv to i32 |
556 ret i32 %conv.ret_ext | 585 ret i32 %conv.ret_ext |
557 } | 586 } |
558 ; CHECK-LABEL: trunc64To8Unsigned | 587 ; CHECK-LABEL: trunc64To8Unsigned |
559 ; CHECK: mov eax, dword ptr [esp+4] | 588 ; CHECK: mov eax, dword ptr [esp + 4] |
560 ; CHECK-NEXT: movzx eax, al | 589 ; CHECK-NEXT: movzx eax, al |
561 ; CHECK-NEXT: ret | 590 ; CHECK-NEXT: ret |
562 ; | 591 ; |
563 ; OPTM1-LABEL: trunc64To8Unsigned | 592 ; OPTM1-LABEL: trunc64To8Unsigned |
564 ; OPTM1: mov eax, dword ptr [esp+ | 593 ; OPTM1: mov eax, dword ptr [esp + |
565 ; OPTM1: movzx eax, | 594 ; OPTM1: movzx eax, |
566 ; OPTM1: ret | 595 ; OPTM1: ret |
567 | 596 |
568 define internal i32 @trunc64To1(i64 %a) { | 597 define internal i32 @trunc64To1(i64 %a) { |
569 entry: | 598 entry: |
570 ; %tobool = icmp ne i64 %a, 0 | 599 ; %tobool = icmp ne i64 %a, 0 |
571 %tobool = trunc i64 %a to i1 | 600 %tobool = trunc i64 %a to i1 |
572 %tobool.ret_ext = zext i1 %tobool to i32 | 601 %tobool.ret_ext = zext i1 %tobool to i32 |
573 ret i32 %tobool.ret_ext | 602 ret i32 %tobool.ret_ext |
574 } | 603 } |
575 ; CHECK-LABEL: trunc64To1 | 604 ; CHECK-LABEL: trunc64To1 |
576 ; CHECK: mov eax, dword ptr [esp+4] | 605 ; CHECK: mov eax, dword ptr [esp + 4] |
577 ; CHECK: and eax, 1 | 606 ; CHECK: and eax, 1 |
578 ; CHECK-NEXT: ret | 607 ; CHECK-NEXT: ret |
579 ; | 608 ; |
580 ; OPTM1-LABEL: trunc64To1 | 609 ; OPTM1-LABEL: trunc64To1 |
581 ; OPTM1: mov eax, dword ptr [esp+ | 610 ; OPTM1: mov eax, dword ptr [esp + |
582 ; OPTM1: and eax, 1 | 611 ; OPTM1: and eax, 1 |
583 ; OPTM1: ret | 612 ; OPTM1: ret |
584 | 613 |
585 define internal i64 @sext32To64(i32 %a) { | 614 define internal i64 @sext32To64(i32 %a) { |
586 entry: | 615 entry: |
587 %conv = sext i32 %a to i64 | 616 %conv = sext i32 %a to i64 |
588 ret i64 %conv | 617 ret i64 %conv |
589 } | 618 } |
590 ; CHECK-LABEL: sext32To64 | 619 ; CHECK-LABEL: sext32To64 |
591 ; CHECK: mov | 620 ; CHECK: mov |
(...skipping 508 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... | |
1100 ; OPTM1: cmp | 1129 ; OPTM1: cmp |
1101 ; OPTM1: jbe | 1130 ; OPTM1: jbe |
1102 | 1131 |
1103 define internal i64 @load64(i32 %a) { | 1132 define internal i64 @load64(i32 %a) { |
1104 entry: | 1133 entry: |
1105 %__1 = inttoptr i32 %a to i64* | 1134 %__1 = inttoptr i32 %a to i64* |
1106 %v0 = load i64* %__1, align 1 | 1135 %v0 = load i64* %__1, align 1 |
1107 ret i64 %v0 | 1136 ret i64 %v0 |
1108 } | 1137 } |
1109 ; CHECK-LABEL: load64 | 1138 ; CHECK-LABEL: load64 |
1110 ; CHECK: mov e[[REGISTER:[a-z]+]], dword ptr [esp+4] | 1139 ; CHECK: mov e[[REGISTER:[a-z]+]], dword ptr [esp + 4] |
1111 ; CHECK-NEXT: mov {{.*}}, dword ptr [e[[REGISTER]]] | 1140 ; CHECK-NEXT: mov {{.*}}, dword ptr [e[[REGISTER]]] |
1112 ; CHECK-NEXT: mov {{.*}}, dword ptr [e[[REGISTER]]+4] | 1141 ; CHECK-NEXT: mov {{.*}}, dword ptr [e[[REGISTER]] + 4] |
1113 ; | 1142 ; |
1114 ; OPTM1-LABEL: load64 | 1143 ; OPTM1-LABEL: load64 |
1115 ; OPTM1: mov e{{..}}, dword ptr [e{{..}}] | 1144 ; OPTM1: mov e{{..}}, dword ptr [e{{..}}] |
1116 ; OPTM1: mov e{{..}}, dword ptr [e{{..}}+4] | 1145 ; OPTM1: mov e{{..}}, dword ptr [e{{..}} + 4] |
1117 | 1146 |
1118 define internal void @store64(i32 %a, i64 %value) { | 1147 define internal void @store64(i32 %a, i64 %value) { |
1119 entry: | 1148 entry: |
1120 %__2 = inttoptr i32 %a to i64* | 1149 %__2 = inttoptr i32 %a to i64* |
1121 store i64 %value, i64* %__2, align 1 | 1150 store i64 %value, i64* %__2, align 1 |
1122 ret void | 1151 ret void |
1123 } | 1152 } |
1124 ; CHECK-LABEL: store64 | 1153 ; CHECK-LABEL: store64 |
1125 ; CHECK: mov e[[REGISTER:[a-z]+]], dword ptr [esp+4] | 1154 ; CHECK: mov e[[REGISTER:[a-z]+]], dword ptr [esp + 4] |
1126 ; CHECK: mov dword ptr [e[[REGISTER]]+4], | 1155 ; CHECK: mov dword ptr [e[[REGISTER]] + 4], |
1127 ; CHECK: mov dword ptr [e[[REGISTER]]], | 1156 ; CHECK: mov dword ptr [e[[REGISTER]]], |
1128 ; | 1157 ; |
1129 ; OPTM1-LABEL: store64 | 1158 ; OPTM1-LABEL: store64 |
1130 ; OPTM1: mov dword ptr [e[[REGISTER:[a-z]+]]+4], | 1159 ; OPTM1: mov dword ptr [e[[REGISTER:[a-z]+]] + 4], |
1131 ; OPTM1: mov dword ptr [e[[REGISTER]]], | 1160 ; OPTM1: mov dword ptr [e[[REGISTER]]], |
1132 | 1161 |
1133 define internal void @store64Const(i32 %a) { | 1162 define internal void @store64Const(i32 %a) { |
1134 entry: | 1163 entry: |
1135 %a.asptr = inttoptr i32 %a to i64* | 1164 %a.asptr = inttoptr i32 %a to i64* |
1136 store i64 -2401053092306725256, i64* %a.asptr, align 1 | 1165 store i64 -2401053092306725256, i64* %a.asptr, align 1 |
1137 ret void | 1166 ret void |
1138 } | 1167 } |
1139 ; CHECK-LABEL: store64Const | 1168 ; CHECK-LABEL: store64Const |
1140 ; CHECK: mov e[[REGISTER:[a-z]+]], dword ptr [esp+4] | 1169 ; CHECK: mov e[[REGISTER:[a-z]+]], dword ptr [esp + 4] |
1141 ; CHECK: mov dword ptr [e[[REGISTER]]+4], 3735928559 | 1170 ; CHECK: mov dword ptr [e[[REGISTER]] + 4], 3735928559 |
1142 ; CHECK: mov dword ptr [e[[REGISTER]]], 305419896 | 1171 ; CHECK: mov dword ptr [e[[REGISTER]]], 305419896 |
1143 ; | 1172 ; |
1144 ; OPTM1-LABEL: store64Const | 1173 ; OPTM1-LABEL: store64Const |
1145 ; OPTM1: mov dword ptr [e[[REGISTER:[a-z]+]]+4], 3735928559 | 1174 ; OPTM1: mov dword ptr [e[[REGISTER:[a-z]+]] + 4], 3735928559 |
1146 ; OPTM1: mov dword ptr [e[[REGISTER]]], 305419896 | 1175 ; OPTM1: mov dword ptr [e[[REGISTER]]], 305419896 |
1147 | 1176 |
1148 define internal i64 @select64VarVar(i64 %a, i64 %b) { | 1177 define internal i64 @select64VarVar(i64 %a, i64 %b) { |
1149 entry: | 1178 entry: |
1150 %cmp = icmp ult i64 %a, %b | 1179 %cmp = icmp ult i64 %a, %b |
1151 %cond = select i1 %cmp, i64 %a, i64 %b | 1180 %cond = select i1 %cmp, i64 %a, i64 %b |
1152 ret i64 %cond | 1181 ret i64 %cond |
1153 } | 1182 } |
1154 ; CHECK-LABEL: select64VarVar | 1183 ; CHECK-LABEL: select64VarVar |
1155 ; CHECK: cmp | 1184 ; CHECK: cmp |
(...skipping 110 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... | |
1266 } | 1295 } |
1267 ; The following checks are not strictly necessary since one of the RUN | 1296 ; The following checks are not strictly necessary since one of the RUN |
1268 ; lines actually runs the output through the assembler. | 1297 ; lines actually runs the output through the assembler. |
1269 ; CHECK-LABEL: icmpLt64Imm | 1298 ; CHECK-LABEL: icmpLt64Imm |
1270 ; CHECK-NOT: cmp {{[0-9]+}}, | 1299 ; CHECK-NOT: cmp {{[0-9]+}}, |
1271 ; OPTM1-LABEL: icmpLt64Imm | 1300 ; OPTM1-LABEL: icmpLt64Imm |
1272 ; OPTM1-NOT: cmp {{[0-9]+}}, | 1301 ; OPTM1-NOT: cmp {{[0-9]+}}, |
1273 | 1302 |
1274 ; ERRORS-NOT: ICE translation error | 1303 ; ERRORS-NOT: ICE translation error |
1275 ; DUMP-NOT: SZ | 1304 ; DUMP-NOT: SZ |
OLD | NEW |