| OLD | NEW |
| 1 // Copyright 2014 the V8 project authors. All rights reserved. | 1 // Copyright 2014 the V8 project authors. All rights reserved. |
| 2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
| 3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
| 4 | 4 |
| 5 #include "src/compiler/code-generator.h" | 5 #include "src/compiler/code-generator.h" |
| 6 | 6 |
| 7 #include "src/arm64/macro-assembler-arm64.h" | 7 #include "src/arm64/macro-assembler-arm64.h" |
| 8 #include "src/compiler/code-generator-impl.h" | 8 #include "src/compiler/code-generator-impl.h" |
| 9 #include "src/compiler/gap-resolver.h" | 9 #include "src/compiler/gap-resolver.h" |
| 10 #include "src/compiler/node-matchers.h" | 10 #include "src/compiler/node-matchers.h" |
| (...skipping 113 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 124 __ asm_instr(i.OutputRegister##width(), i.InputRegister##width(0), imm); \ | 124 __ asm_instr(i.OutputRegister##width(), i.InputRegister##width(0), imm); \ |
| 125 } \ | 125 } \ |
| 126 } while (0); | 126 } while (0); |
| 127 | 127 |
| 128 | 128 |
| 129 // Assembles an instruction after register allocation, producing machine code. | 129 // Assembles an instruction after register allocation, producing machine code. |
| 130 void CodeGenerator::AssembleArchInstruction(Instruction* instr) { | 130 void CodeGenerator::AssembleArchInstruction(Instruction* instr) { |
| 131 Arm64OperandConverter i(this, instr); | 131 Arm64OperandConverter i(this, instr); |
| 132 InstructionCode opcode = instr->opcode(); | 132 InstructionCode opcode = instr->opcode(); |
| 133 switch (ArchOpcodeField::decode(opcode)) { | 133 switch (ArchOpcodeField::decode(opcode)) { |
| 134 case kArchCallAddress: { |
| 135 DirectCEntryStub stub(isolate()); |
| 136 stub.GenerateCall(masm(), i.InputRegister(0)); |
| 137 break; |
| 138 } |
| 139 case kArchCallCodeObject: { |
| 140 if (instr->InputAt(0)->IsImmediate()) { |
| 141 __ Call(Handle<Code>::cast(i.InputHeapObject(0)), |
| 142 RelocInfo::CODE_TARGET); |
| 143 } else { |
| 144 Register target = i.InputRegister(0); |
| 145 __ Add(target, target, Code::kHeaderSize - kHeapObjectTag); |
| 146 __ Call(target); |
| 147 } |
| 148 AddSafepointAndDeopt(instr); |
| 149 // Meaningless instruction for ICs to overwrite. |
| 150 AddNopForSmiCodeInlining(); |
| 151 break; |
| 152 } |
| 153 case kArchCallJSFunction: { |
| 154 // TODO(jarin) The load of the context should be separated from the call. |
| 155 Register func = i.InputRegister(0); |
| 156 __ Ldr(cp, FieldMemOperand(func, JSFunction::kContextOffset)); |
| 157 __ Ldr(x10, FieldMemOperand(func, JSFunction::kCodeEntryOffset)); |
| 158 __ Call(x10); |
| 159 AddSafepointAndDeopt(instr); |
| 160 break; |
| 161 } |
| 162 case kArchDeoptimize: { |
| 163 int deoptimization_id = MiscField::decode(instr->opcode()); |
| 164 BuildTranslation(instr, 0, deoptimization_id); |
| 165 Address deopt_entry = Deoptimizer::GetDeoptimizationEntry( |
| 166 isolate(), deoptimization_id, Deoptimizer::LAZY); |
| 167 __ Call(deopt_entry, RelocInfo::RUNTIME_ENTRY); |
| 168 break; |
| 169 } |
| 170 case kArchDrop: { |
| 171 int words = MiscField::decode(instr->opcode()); |
| 172 __ Drop(words); |
| 173 break; |
| 174 } |
| 134 case kArchJmp: | 175 case kArchJmp: |
| 135 __ B(code_->GetLabel(i.InputBlock(0))); | 176 __ B(code_->GetLabel(i.InputBlock(0))); |
| 136 break; | 177 break; |
| 137 case kArchNop: | 178 case kArchNop: |
| 138 // don't emit code for nops. | 179 // don't emit code for nops. |
| 139 break; | 180 break; |
| 140 case kArchRet: | 181 case kArchRet: |
| 141 AssembleReturn(); | 182 AssembleReturn(); |
| 142 break; | 183 break; |
| 143 case kArchDeoptimize: { | |
| 144 int deoptimization_id = MiscField::decode(instr->opcode()); | |
| 145 BuildTranslation(instr, 0, deoptimization_id); | |
| 146 | |
| 147 Address deopt_entry = Deoptimizer::GetDeoptimizationEntry( | |
| 148 isolate(), deoptimization_id, Deoptimizer::LAZY); | |
| 149 __ Call(deopt_entry, RelocInfo::RUNTIME_ENTRY); | |
| 150 break; | |
| 151 } | |
| 152 case kArchTruncateDoubleToI: | 184 case kArchTruncateDoubleToI: |
| 153 __ TruncateDoubleToI(i.OutputRegister(), i.InputDoubleRegister(0)); | 185 __ TruncateDoubleToI(i.OutputRegister(), i.InputDoubleRegister(0)); |
| 154 break; | 186 break; |
| 155 case kArm64Add: | 187 case kArm64Add: |
| 156 __ Add(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1)); | 188 __ Add(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1)); |
| 157 break; | 189 break; |
| 158 case kArm64Add32: | 190 case kArm64Add32: |
| 159 if (FlagsModeField::decode(opcode) != kFlags_none) { | 191 if (FlagsModeField::decode(opcode) != kFlags_none) { |
| 160 __ Adds(i.OutputRegister32(), i.InputRegister32(0), | 192 __ Adds(i.OutputRegister32(), i.InputRegister32(0), |
| 161 i.InputOperand32(1)); | 193 i.InputOperand32(1)); |
| (...skipping 114 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 276 break; | 308 break; |
| 277 case kArm64Ror32: | 309 case kArm64Ror32: |
| 278 ASSEMBLE_SHIFT(Ror, 32); | 310 ASSEMBLE_SHIFT(Ror, 32); |
| 279 break; | 311 break; |
| 280 case kArm64Mov32: | 312 case kArm64Mov32: |
| 281 __ Mov(i.OutputRegister32(), i.InputRegister32(0)); | 313 __ Mov(i.OutputRegister32(), i.InputRegister32(0)); |
| 282 break; | 314 break; |
| 283 case kArm64Sxtw: | 315 case kArm64Sxtw: |
| 284 __ Sxtw(i.OutputRegister(), i.InputRegister32(0)); | 316 __ Sxtw(i.OutputRegister(), i.InputRegister32(0)); |
| 285 break; | 317 break; |
| 286 case kArm64CallCodeObject: { | |
| 287 if (instr->InputAt(0)->IsImmediate()) { | |
| 288 Handle<Code> code = Handle<Code>::cast(i.InputHeapObject(0)); | |
| 289 __ Call(code, RelocInfo::CODE_TARGET); | |
| 290 } else { | |
| 291 Register reg = i.InputRegister(0); | |
| 292 int entry = Code::kHeaderSize - kHeapObjectTag; | |
| 293 __ Ldr(reg, MemOperand(reg, entry)); | |
| 294 __ Call(reg); | |
| 295 } | |
| 296 | |
| 297 AddSafepointAndDeopt(instr); | |
| 298 // Meaningless instruction for ICs to overwrite. | |
| 299 AddNopForSmiCodeInlining(); | |
| 300 break; | |
| 301 } | |
| 302 case kArm64CallJSFunction: { | |
| 303 Register func = i.InputRegister(0); | |
| 304 | |
| 305 // TODO(jarin) The load of the context should be separated from the call. | |
| 306 __ Ldr(cp, FieldMemOperand(func, JSFunction::kContextOffset)); | |
| 307 __ Ldr(x10, FieldMemOperand(func, JSFunction::kCodeEntryOffset)); | |
| 308 __ Call(x10); | |
| 309 | |
| 310 AddSafepointAndDeopt(instr); | |
| 311 break; | |
| 312 } | |
| 313 case kArm64CallAddress: { | |
| 314 DirectCEntryStub stub(isolate()); | |
| 315 stub.GenerateCall(masm(), i.InputRegister(0)); | |
| 316 break; | |
| 317 } | |
| 318 case kArm64Claim: { | 318 case kArm64Claim: { |
| 319 int words = MiscField::decode(instr->opcode()); | 319 int words = MiscField::decode(instr->opcode()); |
| 320 __ Claim(words); | 320 __ Claim(words); |
| 321 break; | 321 break; |
| 322 } | 322 } |
| 323 case kArm64Poke: { | 323 case kArm64Poke: { |
| 324 int slot = MiscField::decode(instr->opcode()); | 324 int slot = MiscField::decode(instr->opcode()); |
| 325 Operand operand(slot * kPointerSize); | 325 Operand operand(slot * kPointerSize); |
| 326 __ Poke(i.InputRegister(0), operand); | 326 __ Poke(i.InputRegister(0), operand); |
| 327 break; | 327 break; |
| 328 } | 328 } |
| 329 case kArm64PokePairZero: { | 329 case kArm64PokePairZero: { |
| 330 // TODO(dcarney): test slot offset and register order. | 330 // TODO(dcarney): test slot offset and register order. |
| 331 int slot = MiscField::decode(instr->opcode()) - 1; | 331 int slot = MiscField::decode(instr->opcode()) - 1; |
| 332 __ PokePair(i.InputRegister(0), xzr, slot * kPointerSize); | 332 __ PokePair(i.InputRegister(0), xzr, slot * kPointerSize); |
| 333 break; | 333 break; |
| 334 } | 334 } |
| 335 case kArm64PokePair: { | 335 case kArm64PokePair: { |
| 336 int slot = MiscField::decode(instr->opcode()) - 1; | 336 int slot = MiscField::decode(instr->opcode()) - 1; |
| 337 __ PokePair(i.InputRegister(1), i.InputRegister(0), slot * kPointerSize); | 337 __ PokePair(i.InputRegister(1), i.InputRegister(0), slot * kPointerSize); |
| 338 break; | 338 break; |
| 339 } | 339 } |
| 340 case kArm64Drop: { | |
| 341 int words = MiscField::decode(instr->opcode()); | |
| 342 __ Drop(words); | |
| 343 break; | |
| 344 } | |
| 345 case kArm64Cmp: | 340 case kArm64Cmp: |
| 346 __ Cmp(i.InputRegister(0), i.InputOperand(1)); | 341 __ Cmp(i.InputRegister(0), i.InputOperand(1)); |
| 347 break; | 342 break; |
| 348 case kArm64Cmp32: | 343 case kArm64Cmp32: |
| 349 __ Cmp(i.InputRegister32(0), i.InputOperand32(1)); | 344 __ Cmp(i.InputRegister32(0), i.InputOperand32(1)); |
| 350 break; | 345 break; |
| 351 case kArm64Tst: | 346 case kArm64Tst: |
| 352 __ Tst(i.InputRegister(0), i.InputOperand(1)); | 347 __ Tst(i.InputRegister(0), i.InputOperand(1)); |
| 353 break; | 348 break; |
| 354 case kArm64Tst32: | 349 case kArm64Tst32: |
| (...skipping 492 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 847 } | 842 } |
| 848 | 843 |
| 849 | 844 |
| 850 void CodeGenerator::AddNopForSmiCodeInlining() { __ movz(xzr, 0); } | 845 void CodeGenerator::AddNopForSmiCodeInlining() { __ movz(xzr, 0); } |
| 851 | 846 |
| 852 #undef __ | 847 #undef __ |
| 853 | 848 |
| 854 } // namespace compiler | 849 } // namespace compiler |
| 855 } // namespace internal | 850 } // namespace internal |
| 856 } // namespace v8 | 851 } // namespace v8 |
| OLD | NEW |