MIPS: Move register conventions out of the IC classes.

src/ic/mips64/ic-conventions-mips64.cc

Index: src/ic/mips64/ic-conventions-mips64.cc
diff --git a/src/ic/ia32/ic-conventions-ia32.cc b/src/ic/mips64/ic-conventions-mips64.cc
similarity index 53%
copy from src/ic/ia32/ic-conventions-ia32.cc
copy to src/ic/mips64/ic-conventions-mips64.cc
index cef55e9fb1d4f6c313ae4f490cab66ea574f0abb..b42e60b6fb23988838c966c7d4689377390329b8 100644
--- a/src/ic/ia32/ic-conventions-ia32.cc
+++ b/src/ic/mips64/ic-conventions-mips64.cc
@@ -4,7 +4,7 @@
 
 #include "src/v8.h"
 
-#if V8_TARGET_ARCH_IA32
+#if V8_TARGET_ARCH_MIPS64
 
 #include "src/codegen.h"
 #include "src/ic/ic-conventions.h"
@@ -13,28 +13,27 @@ namespace v8 {
 namespace internal {
 
 // IC register specifications
-
-const Register LoadConvention::ReceiverRegister() { return edx; }
-const Register LoadConvention::NameRegister() { return ecx; }
+const Register LoadConvention::ReceiverRegister() { return a1; }
+const Register LoadConvention::NameRegister() { return a2; }
 
 
 const Register VectorLoadConvention::SlotRegister() {
   DCHECK(FLAG_vector_ics);
-  return eax;
+  return a0;
 }
 
 
 const Register FullVectorLoadConvention::VectorRegister() {
   DCHECK(FLAG_vector_ics);
-  return ebx;
+  return a3;
 }
 
 
-const Register StoreConvention::ReceiverRegister() { return edx; }
-const Register StoreConvention::NameRegister() { return ecx; }
-const Register StoreConvention::ValueRegister() { return eax; }
-const Register StoreConvention::MapRegister() { return ebx; }
+const Register StoreConvention::ReceiverRegister() { return a1; }
+const Register StoreConvention::NameRegister() { return a2; }
+const Register StoreConvention::ValueRegister() { return a0; }
+const Register StoreConvention::MapRegister() { return a3; }
 }
 }  // namespace v8::internal
 
-#endif  // V8_TARGET_ARCH_IA32
+#endif  // V8_TARGET_ARCH_MIPS64