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Issue 50863002: Use register allocator for context on x64. (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: added comment to test case Created 7 years, 1 month ago
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1 // Copyright 2012 the V8 project authors. All rights reserved. 1 // Copyright 2012 the V8 project authors. All rights reserved.
2 // Redistribution and use in source and binary forms, with or without 2 // Redistribution and use in source and binary forms, with or without
3 // modification, are permitted provided that the following conditions are 3 // modification, are permitted provided that the following conditions are
4 // met: 4 // met:
5 // 5 //
6 // * Redistributions of source code must retain the above copyright 6 // * Redistributions of source code must retain the above copyright
7 // notice, this list of conditions and the following disclaimer. 7 // notice, this list of conditions and the following disclaimer.
8 // * Redistributions in binary form must reproduce the above 8 // * Redistributions in binary form must reproduce the above
9 // copyright notice, this list of conditions and the following 9 // copyright notice, this list of conditions and the following
10 // disclaimer in the documentation and/or other materials provided 10 // disclaimer in the documentation and/or other materials provided
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302 302
303 303
304 void MacroAssembler::RecordWriteField( 304 void MacroAssembler::RecordWriteField(
305 Register object, 305 Register object,
306 int offset, 306 int offset,
307 Register value, 307 Register value,
308 Register dst, 308 Register dst,
309 SaveFPRegsMode save_fp, 309 SaveFPRegsMode save_fp,
310 RememberedSetAction remembered_set_action, 310 RememberedSetAction remembered_set_action,
311 SmiCheck smi_check) { 311 SmiCheck smi_check) {
312 // The compiled code assumes that record write doesn't change the
313 // context register, so we check that none of the clobbered
314 // registers are rsi.
315 ASSERT(!value.is(rsi) && !dst.is(rsi));
316
317 // First, check if a write barrier is even needed. The tests below 312 // First, check if a write barrier is even needed. The tests below
318 // catch stores of Smis. 313 // catch stores of Smis.
319 Label done; 314 Label done;
320 315
321 // Skip barrier if writing a smi. 316 // Skip barrier if writing a smi.
322 if (smi_check == INLINE_SMI_CHECK) { 317 if (smi_check == INLINE_SMI_CHECK) {
323 JumpIfSmi(value, &done); 318 JumpIfSmi(value, &done);
324 } 319 }
325 320
326 // Although the object register is tagged, the offset is relative to the start 321 // Although the object register is tagged, the offset is relative to the start
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383 } 378 }
384 } 379 }
385 380
386 381
387 void MacroAssembler::RecordWrite(Register object, 382 void MacroAssembler::RecordWrite(Register object,
388 Register address, 383 Register address,
389 Register value, 384 Register value,
390 SaveFPRegsMode fp_mode, 385 SaveFPRegsMode fp_mode,
391 RememberedSetAction remembered_set_action, 386 RememberedSetAction remembered_set_action,
392 SmiCheck smi_check) { 387 SmiCheck smi_check) {
393 // The compiled code assumes that record write doesn't change the
394 // context register, so we check that none of the clobbered
395 // registers are rsi.
396 ASSERT(!value.is(rsi) && !address.is(rsi));
397
398 ASSERT(!object.is(value)); 388 ASSERT(!object.is(value));
399 ASSERT(!object.is(address)); 389 ASSERT(!object.is(address));
400 ASSERT(!value.is(address)); 390 ASSERT(!value.is(address));
401 AssertNotSmi(object); 391 AssertNotSmi(object);
402 392
403 if (remembered_set_action == OMIT_REMEMBERED_SET && 393 if (remembered_set_action == OMIT_REMEMBERED_SET &&
404 !FLAG_incremental_marking) { 394 !FLAG_incremental_marking) {
405 return; 395 return;
406 } 396 }
407 397
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4964 movq(arg_reg_1, isolate, RelocInfo::EXTERNAL_REFERENCE); 4954 movq(arg_reg_1, isolate, RelocInfo::EXTERNAL_REFERENCE);
4965 CallCFunction( 4955 CallCFunction(
4966 ExternalReference::record_object_allocation_function(isolate), 3); 4956 ExternalReference::record_object_allocation_function(isolate), 3);
4967 PopSafepointRegisters(); 4957 PopSafepointRegisters();
4968 } 4958 }
4969 4959
4970 4960
4971 } } // namespace v8::internal 4961 } } // namespace v8::internal
4972 4962
4973 #endif // V8_TARGET_ARCH_X64 4963 #endif // V8_TARGET_ARCH_X64
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