[turbofan] Add backend support for signed loads.

src/compiler/ia32/instruction-codes-ia32.h

 // Copyright 2014 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #ifndef V8_COMPILER_IA32_INSTRUCTION_CODES_IA32_H_
 #define V8_COMPILER_IA32_INSTRUCTION_CODES_IA32_H_
 
 namespace v8 {
 namespace internal {
 namespace compiler {
@@ skipping 25 matching lines @@
   V(SSEFloat64Cmp)                 \
   V(SSEFloat64Add)                 \
   V(SSEFloat64Sub)                 \
   V(SSEFloat64Mul)                 \
   V(SSEFloat64Div)                 \
   V(SSEFloat64Mod)                 \
   V(SSEFloat64ToInt32)             \
   V(SSEFloat64ToUint32)            \
   V(SSEInt32ToFloat64)             \
   V(SSEUint32ToFloat64)            \
-  V(SSELoad)                       \
-  V(SSEStore)                      \
-  V(IA32LoadWord8)                 \
-  V(IA32StoreWord8)                \
-  V(IA32StoreWord8I)               \
-  V(IA32LoadWord16)                \
-  V(IA32StoreWord16)               \
-  V(IA32StoreWord16I)              \
-  V(IA32LoadWord32)                \
-  V(IA32StoreWord32)               \
-  V(IA32StoreWord32I)              \
+  V(IA32Movsxbl)                   \
+  V(IA32Movzxbl)                   \
+  V(IA32Movb)                      \
+  V(IA32Movsxwl)                   \
+  V(IA32Movzxwl)                   \
+  V(IA32Movw)                      \
+  V(IA32Movl)                      \
+  V(IA32Movsd)                     \
   V(IA32StoreWriteBarrier)
 
 
 // Addressing modes represent the "shape" of inputs to an instruction.
 // Many instructions support multiple addressing modes. Addressing modes
 // are encoded into the InstructionCode of the instruction and tell the
 // code generator after register allocation which assembler method to call.
 //
 // We use the following local notation for addressing modes:
 //
@@ skipping 13 matching lines @@
   V(MR1I) /* [%r0 + %r1 * 1 + K] */    \
   V(MR2I) /* [%r0 + %r1 * 2 + K] */    \
   V(MR4I) /* [%r0 + %r1 * 4 + K] */    \
   V(MR8I) /* [%r0 + %r1 * 8 + K] */
 
 }  // namespace compiler
 }  // namespace internal
 }  // namespace v8
 
 #endif  // V8_COMPILER_IA32_INSTRUCTION_CODES_IA32_H_