[turbofan] Add backend support for signed loads.

src/compiler/arm/instruction-codes-arm.h

 // Copyright 2014 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #ifndef V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_
 #define V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_
 
 namespace v8 {
 namespace internal {
 namespace compiler {
@@ skipping 32 matching lines @@
   V(ArmVmulF64)                    \
   V(ArmVmlaF64)                    \
   V(ArmVmlsF64)                    \
   V(ArmVdivF64)                    \
   V(ArmVmodF64)                    \
   V(ArmVnegF64)                    \
   V(ArmVcvtF64S32)                 \
   V(ArmVcvtF64U32)                 \
   V(ArmVcvtS32F64)                 \
   V(ArmVcvtU32F64)                 \
-  V(ArmFloat64Load)                \
-  V(ArmFloat64Store)               \
-  V(ArmLoadWord8)                  \
-  V(ArmStoreWord8)                 \
-  V(ArmLoadWord16)                 \
-  V(ArmStoreWord16)                \
-  V(ArmLoadWord32)                 \
-  V(ArmStoreWord32)                \
+  V(ArmVldr64)                     \
+  V(ArmVstr64)                     \
+  V(ArmLdrb)                       \
+  V(ArmLdrsb)                      \
+  V(ArmStrb)                       \
+  V(ArmLdrh)                       \
+  V(ArmLdrsh)                      \
+  V(ArmStrh)                       \
+  V(ArmLdr)                        \
+  V(ArmStr)                        \
   V(ArmStoreWriteBarrier)
 
 
 // Addressing modes represent the "shape" of inputs to an instruction.
 // Many instructions support multiple addressing modes. Addressing modes
 // are encoded into the InstructionCode of the instruction and tell the
 // code generator after register allocation which assembler method to call.
 #define TARGET_ADDRESSING_MODE_LIST(V)  \
   V(Offset_RI)        /* [%r0 + K] */   \
   V(Offset_RR)        /* [%r0 + %r1] */ \
   V(Operand2_I)       /* K */           \
   V(Operand2_R)       /* %r0 */         \
   V(Operand2_R_ASR_I) /* %r0 ASR K */   \
   V(Operand2_R_LSL_I) /* %r0 LSL K */   \
   V(Operand2_R_LSR_I) /* %r0 LSR K */   \
   V(Operand2_R_ROR_I) /* %r0 ROR K */   \
   V(Operand2_R_ASR_R) /* %r0 ASR %r1 */ \
   V(Operand2_R_LSL_R) /* %r0 LSL %r1 */ \
   V(Operand2_R_LSR_R) /* %r0 LSR %r1 */ \
   V(Operand2_R_ROR_R) /* %r0 ROR %r1 */
 
 }  // namespace compiler
 }  // namespace internal
 }  // namespace v8
 
 #endif  // V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_