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1 // Copyright 2013 the V8 project authors. All rights reserved. | 1 // Copyright 2013 the V8 project authors. All rights reserved. |
2 // | 2 // |
3 // Redistribution and use in source and binary forms, with or without | 3 // Redistribution and use in source and binary forms, with or without |
4 // modification, are permitted provided that the following conditions are | 4 // modification, are permitted provided that the following conditions are |
5 // met: | 5 // met: |
6 // | 6 // |
7 // * Redistributions of source code must retain the above copyright | 7 // * Redistributions of source code must retain the above copyright |
8 // notice, this list of conditions and the following disclaimer. | 8 // notice, this list of conditions and the following disclaimer. |
9 // * Redistributions in binary form must reproduce the above | 9 // * Redistributions in binary form must reproduce the above |
10 // copyright notice, this list of conditions and the following | 10 // copyright notice, this list of conditions and the following |
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220 const CPURegister& reg5, const CPURegister& reg6, | 220 const CPURegister& reg5, const CPURegister& reg6, |
221 const CPURegister& reg7, const CPURegister& reg8) { | 221 const CPURegister& reg7, const CPURegister& reg8) { |
222 int number_of_valid_regs = 0; | 222 int number_of_valid_regs = 0; |
223 int number_of_valid_fpregs = 0; | 223 int number_of_valid_fpregs = 0; |
224 | 224 |
225 RegList unique_regs = 0; | 225 RegList unique_regs = 0; |
226 RegList unique_fpregs = 0; | 226 RegList unique_fpregs = 0; |
227 | 227 |
228 const CPURegister regs[] = {reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8}; | 228 const CPURegister regs[] = {reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8}; |
229 | 229 |
230 for (unsigned i = 0; i < ARRAY_SIZE(regs); i++) { | 230 for (unsigned i = 0; i < arraysize(regs); i++) { |
231 if (regs[i].IsRegister()) { | 231 if (regs[i].IsRegister()) { |
232 number_of_valid_regs++; | 232 number_of_valid_regs++; |
233 unique_regs |= regs[i].Bit(); | 233 unique_regs |= regs[i].Bit(); |
234 } else if (regs[i].IsFPRegister()) { | 234 } else if (regs[i].IsFPRegister()) { |
235 number_of_valid_fpregs++; | 235 number_of_valid_fpregs++; |
236 unique_fpregs |= regs[i].Bit(); | 236 unique_fpregs |= regs[i].Bit(); |
237 } else { | 237 } else { |
238 DCHECK(!regs[i].IsValid()); | 238 DCHECK(!regs[i].IsValid()); |
239 } | 239 } |
240 } | 240 } |
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2657 0x0000000000000001UL, | 2657 0x0000000000000001UL, |
2658 0x0000000100000001UL, | 2658 0x0000000100000001UL, |
2659 0x0001000100010001UL, | 2659 0x0001000100010001UL, |
2660 0x0101010101010101UL, | 2660 0x0101010101010101UL, |
2661 0x1111111111111111UL, | 2661 0x1111111111111111UL, |
2662 0x5555555555555555UL, | 2662 0x5555555555555555UL, |
2663 }; | 2663 }; |
2664 int multiplier_idx = CountLeadingZeros(d, kXRegSizeInBits) - 57; | 2664 int multiplier_idx = CountLeadingZeros(d, kXRegSizeInBits) - 57; |
2665 // Ensure that the index to the multipliers array is within bounds. | 2665 // Ensure that the index to the multipliers array is within bounds. |
2666 DCHECK((multiplier_idx >= 0) && | 2666 DCHECK((multiplier_idx >= 0) && |
2667 (static_cast<size_t>(multiplier_idx) < ARRAY_SIZE(multipliers))); | 2667 (static_cast<size_t>(multiplier_idx) < arraysize(multipliers))); |
2668 uint64_t multiplier = multipliers[multiplier_idx]; | 2668 uint64_t multiplier = multipliers[multiplier_idx]; |
2669 uint64_t candidate = (b - a) * multiplier; | 2669 uint64_t candidate = (b - a) * multiplier; |
2670 | 2670 |
2671 if (value != candidate) { | 2671 if (value != candidate) { |
2672 // The candidate pattern doesn't match our input value, so fail. | 2672 // The candidate pattern doesn't match our input value, so fail. |
2673 return false; | 2673 return false; |
2674 } | 2674 } |
2675 | 2675 |
2676 // We have a match! This is a valid logical immediate, so now we have to | 2676 // We have a match! This is a valid logical immediate, so now we have to |
2677 // construct the bits and pieces of the instruction encoding that generates | 2677 // construct the bits and pieces of the instruction encoding that generates |
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3120 movz(scratch, (target_offset >> 16) & 0xFFFF, 16); | 3120 movz(scratch, (target_offset >> 16) & 0xFFFF, 16); |
3121 movk(scratch, (target_offset >> 32) & 0xFFFF, 32); | 3121 movk(scratch, (target_offset >> 32) & 0xFFFF, 32); |
3122 DCHECK((target_offset >> 48) == 0); | 3122 DCHECK((target_offset >> 48) == 0); |
3123 add(rd, rd, scratch); | 3123 add(rd, rd, scratch); |
3124 } | 3124 } |
3125 | 3125 |
3126 | 3126 |
3127 } } // namespace v8::internal | 3127 } } // namespace v8::internal |
3128 | 3128 |
3129 #endif // V8_TARGET_ARCH_ARM64 | 3129 #endif // V8_TARGET_ARCH_ARM64 |
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