[turbofan] Add backend support for load/store float32 values.

src/compiler/arm64/instruction-selector-arm64.cc

Index: src/compiler/arm64/instruction-selector-arm64.cc
diff --git a/src/compiler/arm64/instruction-selector-arm64.cc b/src/compiler/arm64/instruction-selector-arm64.cc
index 410105c1880b3f0c97534d96c625627993202fd9..46cb7feb5aa0bf66ae4d7a67a41dab44887f96dc 100644
--- a/src/compiler/arm64/instruction-selector-arm64.cc
+++ b/src/compiler/arm64/instruction-selector-arm64.cc
@@ -148,13 +148,16 @@ void InstructionSelector::VisitLoad(Node* node) {
   Node* base = node->InputAt(0);
   Node* index = node->InputAt(1);
 
-  InstructionOperand* result = rep == kRepFloat64
+  InstructionOperand* result = (rep == kRepFloat32 || rep == kRepFloat64)
                                    ? g.DefineAsDoubleRegister(node)
                                    : g.DefineAsRegister(node);
 
   ArchOpcode opcode;
   // TODO(titzer): signed/unsigned small loads
   switch (rep) {
+    case kRepFloat32:
+      opcode = kArm64LdrS;
+      break;
     case kRepFloat64:
       opcode = kArm64LdrD;
       break;
@@ -207,13 +210,16 @@ void InstructionSelector::VisitStore(Node* node) {
   }
   DCHECK_EQ(kNoWriteBarrier, store_rep.write_barrier_kind);
   InstructionOperand* val;
-  if (rep == kRepFloat64) {
+  if (rep == kRepFloat32 || rep == kRepFloat64) {
     val = g.UseDoubleRegister(value);
   } else {
     val = g.UseRegister(value);
   }
   ArchOpcode opcode;
   switch (rep) {
+    case kRepFloat32:
+      opcode = kArm64StrS;
+      break;
     case kRepFloat64:
       opcode = kArm64StrD;
       break;